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參數(shù)資料
| 型號(hào)： | SD-14531F1-455K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| 封裝： | CERAMIC, FP-36 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | SD-14531F1-455K |
7
Data Device Corporation
www.ddc-web.com
SD-14531
angle is determined by the sum of the bits at logic 1. The digital
outputs are valid 150 ns max after HBE or LBE go low and are
high impedance within 100 ns max of HBE or LBE going high.
INHIBIT (INH, PIN 13)
When an Inhibit (INH) input is applied to the SD-14531, the
Output Transparent Latch is locked causing the output data bits
to remain stable while data is being transferred (See FIGURE 9).
The output data bits are stable 0.5
s after INH goes to logic 0.
A logic 0 at the T input of the Inhibit Transparent Latch latches
the data, and a logic 1 applied to T allows the bits to change. This
latch also prevents the transmission of invalid data when there is
an overlap between CB and INH. While the counter is not being
updated, CB is at logic 0 and the INH latch is transparent; when
CB goes to logic 1, the INH latch is locked. If CB occurs after INH
has been applied, the latch will remain locked and its data will not
change until CB returns to logic 0; if INH is applied during CB,
the latch will not lock until the CB pulse is over. The purpose of
the 50 ns delay is to prevent a race condition between CB and
INH where the up-down counter begins to change as an INH is
applied.
An INH input, regardless of its duration, does not affect the con-
verter update. A simple method of interfacing to a computer
asynchronous to CB is: (1) Apply INH; (2) Wait 0.5
s min; (3)
Transfer the data; (4) Release INH.
A logic 1 for the INH enables the output data to be updated. The
time it takes for INH to go to a logic 1 should be 100 ns minimum
before valid data is transferred. To allow the update of the output
data with valid information the INH must remain at a logic 1 for
1
s minimum (See FIGURE 10).
DATA TRANSFERS
Digital output data from the SD-14531 can be transferred to 8-bit
and 16-bit bus systems. For 8-bit systems, the MSB and LSB
bytes are transferred sequentially. For 16-bit systems all bits are
transferred at the same time
DATA TRANSFER TO 8-BIT BUS
FIGURES 11 and 12 show the connections and timing for trans-
ferring data from the SD-14531 to an 8-bit bus.
As can be seen by the timing diagram, the following occurs:
1. The converter INH control is applied and must remain low for
a minimum of 500 ns before valid data is transferred.
2. HBE is set to a low state (logic 0) 350 ns MIN after INH goes
low and must remain low for a minimum of 150 ns before the
MSB data (1-8) is valid and transferred.
TRANSFORMER ISOLATION
Many applications require electrical isolation to the input of the
converter. DDC offers transformers suitable for these applica-
tions, as indicated in TABLE 8. These transformers are connect-
ed as shown in FIGURES 21 and 22.
INTERFACING - DIGITAL OUTPUTS AND CONTROLS
DIGITAL INTERFACE
The digital interface circuitry performs three main functions:
1. Latches the output bits during an Inhibit (INH) command allow-
ing stable data to be read out of the SD-14531.
2. Furnishes parallel tri-state data formats.
3. Acts as a buffer between the internal CMOS logic and the
external TTL logic.
In the SD-14531 applying an Inhibit (INH) command will lock the
data in the inhibit transparent latch without interfering with the
continuous tracking of the converter’s feedback loop. Therefore
the digital angle
φ is always updated, and the INH can be applied
for an arbitrary amount of time. The Inhibit Transparent Latch and
the 50 ns delay are part of the inhibit circuitry. For further infor-
mation see the INHIBIT (INH, PIN 13) paragraph.
DIGITAL ANGLE OUTPUTS (LOGIC INPUT/OUTPUT)
The digital angle outputs are buffered and provided in a two-byte
format. The first byte contains the MSBs (bits 1-8) and is enabled
by placing HBE (pin 35) to a logic 0. Depending on the user-pro-
grammed resolution, the second byte contains the LSBs and is
enabled by placing LBE (pin 17) to a logic 0.
The second byte will contain either bits 9-14 (14-bit resolution) or
bits 9-16 (16-bit resolution). All unused LSB’s will be at logic 0.
TABLE 3 lists the angular weight for the digital angle outputs.
The digital angle outputs are valid 150 ns after HBE or LBE are
activated with a logic 0 and are high impedance within 100 ns,
max after HBE and LBE are set to logic 1 (See FIGURE 7). Both
enables are internally pulled down.
DIGITAL ANGLE OUTPUT TIMING
The digital angle output is 14 or 16 parallel data bits and
Converter Busy (CB). All logic outputs are short-circuit proof to
ground and +5 V. The CB output is a positive, 0.8 to
3.0
s pulse.
The digital output data changes approximately 50 ns after the
leading edge of the CB pulse because of an internal delay. Data
is valid 0.2
s after the leading edge of CB (See FIGURE 8). The
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| SD-14531F1-455Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F1-455Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F1-462K | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F1-462L | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F1-462Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
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