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參數(shù)資料
2
Data
De
vice
Cor
por
ation
www
.d
dc-web.com
SD-14590/91/92
D-02/02-250
FIGURE 1. SD-14590/91/92 BLOCK DIAGRAM
S1
S2
S3
SOLID STATE SYNCHRO INPUT OPTION
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
SOLID STATE RESOLVER INPUT OPTION
RESOLVER
CONDITIONER
SIN
θ
COS
θ
S4
DIRECT INPUT OPTION
VOLTAGE
FOLLOWER
BUFFER
SIN
θ
COS
θ
SIN
θ
COS
θ
INPUT OPTIONS
V
INTERNAL
DC
REFERENCE
CONDITIONER
SYNTHESIZED
REF
DEMOD
BIT DETECT
ERROR
PROCESSOR
HIGH ACCURACY
CONTROL
TRANSFORMER
INPUT OPTION
16 BIT CT
TRANSPARENT
LATCH
16 BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
3 STATE
TTL BUFFER
16 BIT U-D
COUNTER
EDGE
TRIGGERED
LATCH
VCO
INHIBIT
TRANSPARENT
LATCH
POWER
SUPPLY
CONDITIONER
DIGITAL
ANGLE
φ
+5 V
INH
EM
BITS 1-8
BITS 9-14/16
EL
RESOLUTION CONTROL
T
50 ns DELAY
0.4-1 s
+10 V
INTERNAL DC
REF V (+5 V)
+15V
INH
CB
VEL
e
BIT
+15 V
UNITY
GAIN
BUFFER
VEL
U
T
E
D
R
U
T
GAIN
e
SIN
(
θ-φ)
1 LSB ANTIJITTER FEEDBACK
REF IN
RL
RH
SIN
θ
COS
θ
Q
A
GND
UNITY
GAIN
BUFFER
(14590 ONLY)
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