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參數(shù)資料
| 型號(hào)： | SD-14597F3-182W |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| 封裝： | CERAMIC, FP-36 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 416K |
| 代理商： | SD-14597F3-182W |
BIT will also be set for a Loss-of-Signal (LOS) and/or a Loss-of-
Reference (LOR).
PROGRAMMABLE RESOLUTION (14B, PIN 16)
Resolution is controlled by one logic input,14B. The resolution
can be changed during converter operation so the appropriate
resolution and velocity dynamics can be changed as needed. To
insure that a race condition does not exist between counting and
changing the resolution, input 14B is latched internally on the
trailing edge of CB (see FIGURE 2).
Note: The SD-14595 has programmable resolution whereas the
SD-14596 and 97 do not.
INTERFACING - INPUTS
SIGNAL INPUT OPTIONS
The SD-14595/96/97 series offers direct synchro or resolver
inputs. In a synchro or resolver, shaft angle data is transmitted as
the ratio of carrier amplitudes across the input terminals.
Synchro signals, which are of the form sin
θcosωt, sin(θ+120°)
cos
ωt, and sin(θ+240°)cosωt are internally converted to resolver
format, sin
θcosωt and cosθcosωt.
FIGURE 3 illustrates synchro and resolver signals as a function
of the angle
θ.
The solid-state signal and reference inputs are true differential
inputs with high ac and dc common mode rejection.
Input imped-
ance is maintained with power off.
4
ence signal from the sin
θ - cos(ωt + α), cosθ - cos(ωt + α) signal
inputs and from the cos
ωt reference input. The phase angle of
the synthesized reference is determined by the signal input. The
reference input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
phase with the signal input, and quadrature errors will therefore
be eliminated. The synthesized reference circuit also elimi-
nates the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Magnitude of Error=(Quadrature Voltage/Full Scale (FS).signal) tan(
α)
Where:
Magnitude of Error is in radians.
Quadrature Voltage is in volts.
Full Scale signal is in volts.
α = signal to REF phase shift
An example of the magnitude of error is as follows:
Let:
Quadrature Voltage = 11.8 mV
Let:
FS signal = 11.8 V
Let:
α = 6°
Then: Magnitude of Error = 0.35 min
1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed volt-
age which is determined by the following formula:
Speed Voltage=(rotational speed/carrier frequency) FS signal
Where:
Speed Voltage is the quadrature due to rotation.
Rotational speed is the rps (rotations per second) of the
synchro or resolver.
Carrier frequency is the REF in Hz.
BUILT-IN-TEST (BIT, PIN 15)
The Built-In-Test output (BIT) monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero. If it exceeds approxi-
mately 180 LSBs (of the selected resolution) the logic level at
BIT will change from a logic 0 to logic 1. This condition will occur
during a large step and reset after the converter settles out. BIT
will also change to logic 1 for an over-velocity condition, because
the converter loop cannot maintain input-output and/or if the con-
verter malfunctions where it cannot maintain the loop at a null.
,,,
,,
14B
0
s MIN
CB
0.1
s MIN
30
90
150
210
270
330
360
θ
(DEGREES)
CCW
In
Phase
with
RL-RH
of
Converter
and
R2-R1
of
CX.
0
S1-S3 = V
SIN
θ
MAX
S3-S2 = V
SIN(
θ + 120°)
MAX
S2-S1 = V
SIN(
θ + 240°)
MAX
- V
MAX
+ V
MAX
30
90
150
210
270
330
360
θ
(DEGREES)
CCW
In
Phase
with
RH-RL
of
Converter
and
R2-R4
of
RX.
0
S2-S4 = V
COS
θ
MAX
S1-S3 = V
SIN(
θ)
MAX
- V
MAX
+ V
MAX
FIGURE 2. RESOLUTION CONTROL TIMING DIAGRAM
Standard Resolver Control Transmitter (RX) Outputs as a Function of CCW
Rotation From Electrical Zero (EZ) With R2-R4 Excited.
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
FIGURE 3. SYNCHRO AND RESOLVER SIGNALS
相關(guān)PDF資料 |
PDF描述 |
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| SD-14597F3-184L | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14597F3-184Q | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14597F3-184S | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14597F3-184Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
| SD-14597F3-184Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SD-14597F3-202 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SD-14597F3-204 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SD-14597F3-205 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SD-14597F3-302 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
| SD-14597F3-304 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchro-to-Digital Converter |
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