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參數(shù)資料
| 型號(hào)： | sda 9254-2 |
| 廠商： | SIEMENS AG |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter(應(yīng)用于TV的2.6 M位動(dòng)態(tài)存儲(chǔ)器) |
| 中文描述： | 2.6兆比特的動(dòng)態(tài)影視順序訪問應(yīng)用程序的內(nèi)存（電視，SAM）的具有片上降噪過濾器（應(yīng)用于電視的260萬位動(dòng)態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 31/32頁 |
| 文件大小： | 182K |
| 代理商： | SDA 9254-2 |
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SDA 9254-2
Semiconductor Group
31
1998-01-16
Application Information
Digital Storage of a TV Field
As standard for digital TV systems, CCIR recommendation 601 defines a field of 288 lines with
720 pixels per line. The sampling frequency is 13.5 MHz with a resolution of 8 bit per pixel.
Information is stored in 3 different channels: one channel for luminance (Y), two channels for
chrominance (U and V).
The bandwidth ratio between the different channels is either Y:U:V = 4:1:1 or 4:2:2 depending on
the coding method.
The bus width for the 4:1:1 format is 12 bit, the 4:2:2 format requires 16 bit and a SDA 9251-2X
memory device additionally.
The SDA 9254-2 is designed for low cost large area flicker- and noise reduction systems. The
following block diagram shows a typical application for 4:1:1 signals.
Figure 9
Low Cost Flicker- and Noise Reduction System with SDA 9254-2
UEB08607
Display
Processor
SDA 9280
VOUT
UOUT
YOUT
SDA 9254-2
12
SDA 9220-5
MSC
Address
SYNC
CVBS
YIN
CSG
+
12
Triple ADC
SDA 9206
UIN
VIN
SYNC
To Deflection
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDA9254-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
| SDA9255 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:SRC-Scan Rate Converter SDA9255 |
| SDA9257 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Clock Sync Generator |
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| SDA9280 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:ICs for Consumer Electronics |
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