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參數(shù)資料
| 型號： | SDC-14535-102 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP32 |
| 封裝： | TDIP-32 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 421K |
| 代理商： | SDC-14535-102 |
2
11.8 V L-L
17.5k Ohm
11.5k Ohm
TABLE 1. SDC-14532 SPECIFICATIONS
Apply over temperature range, power supply range, reference fre-
quency, and amplitude ranges: 10% signal amplitude variation; and
up to 10% harmonic distortion in reference.
PARAMETER
VALUE
RESOLUTION
12 or 14 bits
ACCURACY
±8.5 min (12 bit)
±5.3 min (14 bit)
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Range
Voltage Range
Input Impedance
Single Ended
Differential
Common Mode Range
360 to 2600 Hz
4 to 130 Vrms
250k Ohm min
500k Ohm min
210 V peak max, 500 V transient peak
SIGNAL INPUT
CHARACTERISTICS
(Voltage options and mini-
mum input impedance
balanced)
Synchro
90 V L-L
Zin Line-to-Line
Zin Each Line to Ground
130k Ohm
85k Ohm
Zin Single Ended
Zin Differential
Zin Each Line to Ground
Common Mode Range
23k Ohm
46k Ohm
23k Ohm
25 V max
11.8 V L-L
Resolver
26 V L-L
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Inhibit (INH)
Enable bits 1 to 8 (EM)
Enable bits 9 to 12 (EL)
or bits 9 to 14
Output Parallel Data
Converter Busy (CB)
Drive Capability
Built-In-Test (BIT)
TTL/CMOS compatible
Logic 0=0.8 V max
Logic 1=2.0 V min
Loading=30A max pull-up current
source to +5V/5pF max, CMOS
transient protected.
Logic 0 inhibits, data stable after 0.5s
Logic 0 enables, logic 1 high Z.
12 or 14 parallel lines, natural binary
angle, positive logic.
0.4 to 2s positive pulse; leading edge
initiates counter update.
50pF plus rated logic drive.
Logic 0: 1 TTL load, 1.6mA at 0.4V max
Logic 1: 10 TTL loads, 0.4mA at 2.8V
min.
High Z: 10A//5pF max
Logic 1: +5V supply minus 100mV min
driving CMOS.
Logic 0 for fault condition
DYNAMIC
CHARACTERISTICS
See Table 3.
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Range
Max Voltage w/o Damage
Current
+15 V
+5 V
±5%
±10%
+18 V
+8 V
25mA max
10mA max
TEMPERATURE RANGES
Operating
-3XX
-1XX
Storage
0° to +70°C
-55° to +125°C
-65° to +150°C
TABLE 1. SDC-14532 SPECIFICATIONS (CONTINUED)
PARAMETER
VALUE
PHYSICAL
CHARACTERISTICS
Size
Weight
1.74 x 1.14 x 0.28 in.
(44 x 29 x 7.1 mm)
0.8 max (23 gm)
TECHNICAL INFORMATION
The information in this section describes the structures and
operation of the SDC-14532 Series.
INTRODUCTION
The circuit shown in the block diagram of Figure 1 contains two
main parts: a Feedback Loop, whose elements are the control
transformer, demodulator, error processor, VCO and up-down
counter; and Digital Interface circuitry including various latches
and buffers.
SIGNAL INPUTS
The SDC-14532 offers two input options: synchro or resolver. In
a synchro or resolver, shaft angle data is transmitted as the
ratio of carrier amplitudes across the input terminals. Synchro
signals, which are of the form sin
θcosωt, sin(θ + 120°)cosωt,
and sin(
θ +240°)cosωt are internally converted to resolver for-
mat; sin
θcosωt and cosθcosωt (see FIGURE 2).
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection. Input
impedance is maintained with power off.
FEEDBACK LOOP
The Feedback Loop produces a digital angle
φ which tracks the
analog input angle
θ to within the specified accuracy of the con-
verter. The control transformer performs the following trigono-
metric computation:
sin(
θ φ) = sinθ cosφ - cosθ sinφ
where:
θ is the angle theta, representing the resolver shaft position.
φ is the digital angle phi contained in the up/down counter.
The tracking process consists of continually adjusting
φ to make
(
θ φ) → 0, so that φ will represent the shaft position θ. The
output of the demodulator is an analog DC level proportional to
sin (
θ φ). The error processor receives its input from the
demodulator and integrates this sin(
θ φ) error signal which
then drives a Voltage-Controlled Oscillator (VCO). The VCO’s
clock pulses are accumulated by the up-down counter. The
velocity voltage accuracy, linearity and offset are determined by
the quality of the VCO. Functionally, the up-down counter is an
incremental integrator. Therefore, there are two stages of inte-
gration which make the converter a Type II tracking servo. In a
Type II servo, the VCO always settles to a counting rate which
makes d
θ/dt without a lag. The output data will always be fresh
and available as long as the maximum tracking rate of the con-
verter is not exceeded.
50k Ohm
100k Ohm
50k Ohm
60 V max
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