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參數(shù)資料
| 型號： | SDC-14537-312 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP32 |
| 封裝： | TDIP-32 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 421K |
| 代理商： | SDC-14537-312 |
4
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT
DEG/BIT
MIN/BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
180.0
90.0
45.0
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10800.0
5400.0
2700.0
1350.0
675.0
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: EM enables the MSBs and EL enables the LSBs.
Digital angle outputs are buffered and provided in a two-byte
format. The first byte always contains the MSBs (bits 1-8) and
is enabled by placing EM (pin 26) to logic 0. Depending on the
user-programmed resolution, the second byte will have bits 9
through 12 or 9 through 14, while operating at 12- or 14-bit res-
olution, respectively. Placing EL (pin 25) to logic 0 enables the
second byte (the LSBs). A logic 0 will be present on all the
unused least significant bits. TABLE 2 lists the deg/bit for the
digital angle outputs.
As long as the converter’s maximum tracking rate is not
exceeded there will be no velocity lag in the converter output,
although momentary acceleration errors remain. If a step input
occurs, as when the power is initially applied, the response will
be critically damped. FIGURE 5 shows the response to a step
input.
After initial slewing at the maximum tracking rate of the convert-
er there is one overshoot, which is inherent in a Type II servo.
The overshoot settling to a final value is a function of the small
signal settling time.
OVERSHOOT
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
θ2
θ1
SETTLING TIME
FIGURE 5. RESPONSE TO A STEP INPUT
DYNAMIC PERFORMANCE
A Type II servo loop (Kv = 4) and very high acceleration con-
stants give the SDC-14532 superior dynamic performance, as
listed in TABLE 3. If the power supply voltages are not the +15V
DC nominal values, the specified input rates will increase or
decrease in proportion to the fractional change in voltage. A
Control Loop Block Diagram is show in FIGURE 6, and an Open
Loop Bode Plot is shown in FIGURE 7. The values of the trans-
fer function coefficients are shown in TABLE 3.
ERROR PROCESSOR
INPUT
θ
Open Loop Transfer function = Output
WHERE:
2
A = A A
1
2
VELOCITY
OUT
DIGITAL
POSITION
OUT
(
φ)
VCO
CT
S
A
+ 1
1
B
S
+ 1
10B
H = 1
S
A
+ 1
1
B
2
S
+ 1
10B
+
-
e
A
2
S
2.75
FIGURE 6. CONTROL LOOP BLOCK DIAGRAM
-12
db/oct
BA
2A
-6 db/oct
10B
ω (rad/sec)
(B = A/2)
GAIN = 0.4
GAIN = 4
(CRITICALLY DAMPED)
OPEN LOOP
FIGURE 7. OPEN LOOP BODE PLOT
TABLE 3. DYNAMIC CHARACTERISTICS
PARAMETER
UNITS
Resolution
Input Frequency
Tracking Rate
Bandwidth
Ka
A1
A2
A
B
Settling Time
Bits
Hertz
RPS min
Hertz
1/sec2 nom
1/sec nom
ms max
12
360-2600
48
135
90K
2.05
44K
300
150
90
14
360-2600
12
135
90K
2.05
44K
300
150
2
,
DEPENDS ON d
φ/dt
0.4-2.0
s
CB
0.2
s
DATA
VALID
6.1
s MIN
FIGURE 4. CONVERTER BUSY TIMING DIAGRAM
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