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參數(shù)資料
| 型號： | SDC-14561-225S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | 1.900 X 0.780 INCH, 0.210 INCH HEIGHT, DOUBLE WIDTH, KOVAR, DIP-36 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 196K |
| 代理商： | SDC-14561-225S |
INTRODUCTION
The circuit shown in FIGURE 1, the SDC-14560 Block Diagram,
consists of three main parts: the signal input; a feedback loop,
whose elements are the control transformer, demodulator, error
processor, VCO and up-down counter; and digital interface cir-
cuitry including various latches and buffers.
SIGNAL INPUTS
The SDC-14560 series offers three input options: synchro,
resolver, and direct. In a synchro or resolver, shaft angle data is
transmitted as the ratio of carrier amplitudes across the input ter-
minals. Synchro signals, which are of the form sin
θcosωt,
sin(
θ + 120°)cosωt, and sin(θ + 240°)cosωt are internally con-
verted to resolver format; sin
θcosωt and cosθcosωt. Direct inputs
accept
1 Vrms inputs in resolver form, (sin
θcosωt and cosθ
cos
ωt) and are buffered prior to conversion. FIGURE 2 illustrates
synchro and resolver signals as a function of the angle
θ.
The solid state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection.
Input
impedance is maintained with power off.
3
TABLE 1. SDC-14560 SPECIFICATIONS (CONTD)
PARAMETER
UNIT
VALUE
TRANSFORMERS
CHARACTERISTICS (contd)
Signal Transformer
Carrier Frequency Range
Breakdown Voltage to GND
Minimum Input Impedances
(Balanced)
90 V L-L
26 V L-L
11.8 V L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common-Mode Voltage
Output Description
Output Voltage
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
Output Voltage
Power Required
360- 1000 Hz
700 V peak
Synchro ZIN(ZSO) Resolver ZlN
180
100k
-
30k
20k
30k
47 - 440 Hz
80 - 138 V rms; 115 V rms
nominal resistive
600 k
min resistive
500 V rms transformer isolated
+R (in phase with RH-RL)
and - R (in phase with RL- RH)
derived from op-amps. Short
Circuit proof.
3.0 V nominal riding on ground
reference V. Output Voltage level
tracks input level.
4 mA typ, 7 mA max from
+15 V supply.
47 - 440 Hz
10 - 100 V rms L-L; 90 V rms
L- L nominal
148 k
min L-L balanced
resistive
±500 V rms transformer isolated
Resolver output,
- sine (- S) + cosine (+C)
derived from op-amps.
Short circuit proof.
1.0 V rms nominal riding on
ground reference V.
Output voltage level tracks
input level.
4 mA typ, 7 mA max from
+15 V supply.
Note:
(1) Pin programmable.
(2) See TABLE 6.
30
90
150
210
270
330
360
θ
(DEGREES)
CCW
In
Phase
with
RL-RH
of
Converter
and
R2-R1
of
CX.
0
S1-S3 = V
SIN
θ
MAX
S3-S2 = V
SIN(
θ + 120°)
MAX
S2-S1 = V
SIN(
θ + 240°)
MAX
- V
MAX
+ V
MAX
30
90
150
210
270
330
360
θ
(DEGREES)
CCW
In
Phase
with
RH-RL
of
Converter
and
R2-R4
of
RX.
0
S2-S4 = V
COS
θ
MAX
S1-S3 = –V
SIN(
θ)
MAX
- V
MAX
+ V
MAX
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
FIGURE 2. SYNCHRO AND RESOLVER SIGNALS
Standard Resolver Control Transmitter (RX) Outputs as a Function of CCW
Rotation From Electrical Zero (EZ) With R2-R4 Excited.
SOLID-STATE BUFFER INPUT PRODUCTION -
TRANSIENT VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection, so most applica-
tions will not require units with isolation transformers. Input
impedance is maintained with power off. The current AC peak
+DC common mode voltage should not exceed the values in
TABLE 1.
The 90 V line-to-line systems may have voltage transients which
exceed the 500 V specification. These transients can destroy the
thin-film input resistor network in the hybrid. Therefore, 90 VL-L
solid-state input modules may be protected by installing voltage
suppressors as shown. Voltage transients are likely to occur
whenever synchro or resolver are switched on and off. For
instance, a 1000 V transient can be generated when the prima-
ry of a CX or TX driving a synchro or resolver input is opened.
See FIGURE 3.
FEEDBACK LOOP
The feedback loop produces a digital angle
φ which tracks the
analog input angle
θ to within the specified accuracy of the con-
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