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參數(shù)資料
| 型號(hào)： | SDC-14561-551Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | 1.900 X 0.780 INCH, 0.210 INCH HEIGHT, DOUBLE WIDTH, KOVAR, DIP-36 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 196K |
| 代理商： | SDC-14561-551Q |
verter. The control transformer performs the following trigono-
metric computation:
sin(
θ - φ) = sinθ cosφ - cosθ sinφ
where
θ is the angle representing the resolver shaft position, and
φ is the digital angle contained in the up/down counter. The track-
ing process consists of continually adjusting
φ to make (θ - φ) à
0, so that
φ will represent the shaft position θ. The output of the
demodulator is an analog DC level proportional to sin(
θ - φ). The
error processor receives its input from the demodulator and inte-
grates this sin(
θ - φ) error signal which then drives a Voltage-
Controlled Oscillator (VCO). The VCO’s clock pulses are accu-
mulated by the up/down counter. The velocity voltage accuracy,
linearity and offset are determined by the quality of the VCO.
Functionally, the up/down counter is an incremental integrator.
Therefore, there are two stages of integration which make the
converter a Type II tracking servo. In a Type II servo, the VCO
always settles to a counting rate which makes d
φ/dt equal to
d
θ/dt without a lag. The output data will always be fresh and
available as long as the maximum tracking rate of the converter
is not exceeded.
SYNTHESIZED REFERENCE
The synthesized reference section of the SDC-14560 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals lead the reference signal
(RH and RL) by about 6°. When an uncompensated reference
signal is used to demodulate the control transformer’s output,
quadrature voltages are not completely eliminated. In a 12- or
14-bit converter it is not necessary to compensate for the refer-
ence signal’s phase shift. A 6° phase shift will, however, cause
problems for the one minute accuracy converters. As shown in
FIGURE 1, the converter synthesizes its own cos(
ωt + α) refer-
ence signal from the sin
θcos(ωt + α), cosθcos(ωt + α) signal
inputs and from the cos
ωt reference input. The phase angle of
the synthesized reference is determined by the signal input The
reference input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
phase with the signal input, and quadrature errors will therefore
be eliminated. The synthesized reference circuit also eliminates
the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Error = Quad/F.S. signal * tan(
α)
Where: Error is in radians
Quad/F.S. signal is per unit quadrature input level.
α = signal to reference phase shift in degrees.
A typical example of the magnitude of this source of error is as
follows:
Quad/F.S. signal = .001
α = 6
Error = 0.35 min
≈1 LSB in the 16th bit.
Note: Quad/F.S. is composed of static quadrature which is spec-
ified by the resolver or synchro supplier plus the speed voltage
which is given by:
Speed Voltage = rotational speed/carrier frequency
Where: Speed Voltage is the per unit ratio of electrical rotational
speed in RPS divided by carrier frequency in Hz.
This error is totally negligible for up to 14-bit converters. For 16-
bit converters, where the highest accuracy possible is needed
and where the quadrature and phase shift specifications can be
higher, this source of error could be significant. The reference
synthesizer circuit in the converter which derives the reference
from the input signal essentially sets
α to zero resulting in com-
plete rejection of the quadrature.
DIGITAL INTERFACE
The digital interface circuitry has three main functions: to latch
the output bits during an inhibit command so that the stable data
can be read; to furnish both parallel and three-state data formats;
and to act as a buffer between the internal CMOS logic and the
external TTL logic.
In the SDC-14560, applying an inhibit command will lock the
data in the transparent latch without interfering with the continu-
ous tracking of the feedback loop. Therefore, the digital angle is
always updated, and the inhibit can be applied for an arbitrary
amount of time. The inhibit transparent latch and the 50 ns delay
are part of the inhibit circuitry. The inhibit circuitry is described in
detail in the logic input/output section.
LOGIC INPUT/OUTPUT
Logic angle outputs consist of 10, 12, 14 or 16 parallel data bits
and CONVERTER BUSY (CB). All logic outputs are short-circuit
proof to ground and +5 Volts. The CB output is a positive, 0.4 to
1.0 s pulse. Data changes about 50 ns after the leading edge of
the pulse because of an internal delay. Data is valid 0.2 s after
the leading edge of CB, the angle is determined by the sum of
the bits at logic “1”. Digital outputs are three-state and two bytes
wide; bits 1-8 (MSBs) are enabled by the signal EM, bits 9-16
4
HYBRID
S3
S2
S1
RH
RL
CR1
CR2
S1
FOR 90 V SYNCHRO INPUTS
1N6071A
CR3
S2
S3
HYBRID
S3
S2
S1
S4
FOR 90 V RESOLVER INPUTS
CR4
CR5
S3
S2
S1
S4
90 V L-L
RESOLVER
INPUT
FIGURE 3. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
CR4 and CR5 are 1N6136A, bipolar transient voltage suppressors or equivalent.
CR1, CR2, and CR3 are 1N6136A, bipolar transient voltage suppressors
or equivalent.
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