參數(shù)資料
型號(hào)： SDC-14563-491Y
廠商： DATA DEVICE CORP
元件分類： 位置變換器
英文描述： SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36
封裝： 1.900 X 0.780 INCH, 0.210 INCH HEIGHT, DOUBLE WIDTH, KOVAR, DIP-36
文件頁(yè)數(shù)： 5/12頁(yè)
文件大?。?/td> 196K
代理商： SDC-14563-491Y
2
TABLE 1. SDC-14560 SPECIFICATIONS
Apply over temperature range power supply range reference frequency
and amplitude ranges; 10% signal amplitude variation; and up to 10%
harmonic distortion in the reference.
PARAMETER
UNIT
VALUE
RESOLUTION(1)
ACCURACY(2)
REPEATABILITY
DIFFERENTIAL LINEARITY
Bits
Min
LSB
10, 12, 14, or 16
±6, ±4, ±2, or ±1 +1LSB
1 max
1 max in the 16th bit
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Ranges
Nominal 400 Hz Units
Nominal 60 Hz Units
Voltage Range
Input Impedance
Single Ended
Differential
Common Mode Range
Hz
Vrms
Ohm
V
360-1000
47-1000
4-130
250k min
500k min
210 peak max
500 transient peak
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance balanced)
Synchro
Zin Line to Line
Zin Each Line to Gnd
Resolver
Zin Single Ended
Zin Differential
Zin Each Line to Gnd
Common Mode Range
Direct (1.0 VL-L)
Input Signal Type
sin/cos Voltage Range
Max Voltage w/o Damage
Input Impedance
Ohm
V
Vrms
Ohm
11.8 VL-L
90 VL-L
17.5k
130k
11.5k
85k
11.8 VL-L
26 VL-L
23k
50k
46k
100k
23k
50k
60 max
sin and cos resolver signals
referenced to converter inter-
nal DC reference V.
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M//10 pF
voltage follower
REFERENCE SYNTHESIZER
±Sig/Ref Phase Shift
Deg
60 max, 45 typ
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
S (Control Transformer)
Resolution Control (A & B)
(Unused Output Data
Bits Are Set to 0)
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 A max P.U.
current source
to +5 V//5 pF max
CMOS transient protected
Logic 0 inhibits
Data stable after 0.5 s
Logic 0 enables
Logic 1 High Z
Logic 0 enables
Logic 1 High Z
Logic 0 for use as CT
B
A
Resolution
0
10 bits
0
1
12 bits
1
0
14 bits
1
16 bits
TABLE 1. SDC-14560 SPECIFICATIONS (CONTD)
PARAMETER
UNIT
VALUE
Output Parallel Data
Converter Busy (CB)
BIT
Drive Capability
bits
10, 12, 14, or 16 parallel
lines; natural binary angle,
positive logic
0.4 to 1 s positive pulse;
leading edge initiates
counter update.
Logic 0 for fault.
50 pF plus rated logic drive.
Logic 0; 1 TTL load,
1.6 mA at 0.4 Vmax
Logic 1; 10 TTL loads
0.4 mA at 2.8 V min
High Z; 10 A//5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply minus
100 mV min driving CMOS
ANALOG OUTPUTS
Velocity (VEL)
AC error (e)
Load
mV rms
kOhm
See TABLES 3 and 4
50 per LSB of error
(10-bit mode)
25 per LSB of error
(12-bit mode)
12.5 per LSB of error
(14-bit mode)
6.3 per LSB of error
(16-bit mode)
3 min
DYNAMIC
CHARACTERISTICS
See TABLE 3.
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Range
Max Voltage w/o Damage
Current
±%
V
mA max
+15 V
+5 V
-15 V
510
5
+18
+8
-18
25
10
15
THERMAL RESISTANCE
Junction to Case,
θjc
Junction to Ambient,
θja
TEMPERATURE RANGES
Operating
-30X
-10X
Storage
°C/W
°C
8
20
0 to +70
-55 to +125
-65 to +150
PHYSICAL
CHARACTERISTICS
Size
Weight
in. (mm)
oz. (g)
1.9 x 0.78 x 0.21
(48.3 x 19.8 x 5.3)
36-Pin Double Dip
0.7 max (20)
TRANSFORMERS
CHARACTERISTICS
(See ordering information for
list of Transformers. Reference
Transformers are Optional for
Both Solid-State and Voltage
Follower Input Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
360 - 1000 Hz
18 - 130 V
40 k
min
1200 V peak
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