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參數(shù)資料
| 型號： | SDC-14577-464 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, QMA26 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 377K |
| 代理商： | SDC-14577-464 |
4
BIT, BUILT-IN-TEST
This output is a logic line that will flag an internal fault condition
or LOS (Loss-Of-Signal). The internal fault detector monitors the
internal error and, when it exceeds ±100 LSBs, will set the line
to a logic 0; this condition will occur during a large-step input and
will reset to a logic 1 after the converter settles out. (The error
voltage is filtered with a 500 s filter) BIT will set for an overve-
locity condition because the converter loop cannot maintain
input/output sync. BIT will also set if a total LOS (loss of all sig-
nals) occurs.
NO FALSE 180° HANGUP
This feature eliminates the “false 180° reading” during instanta-
neous 180° step changes; this condition most often occurs when
the input is “electronically switched” from a digital-to-synchro
converter. If the “MSB” (or 180° bit) is “toggled” on and off, a con-
verter without the “false 180° hangup” feature may fail to
respond.
The condition is artificial, as a “real” synchro or resolver cannot
change its output 180° instantaneously. The condition is most
often noticed during wraparound verification tests, simulations,
or troubleshooting.
,
ENABLE
150 ns MAX
DATA
VALID
100 ns MAX
HIGH Z
,,,,,,
DATA
VALID
500 ns MAX
INHIBIT
0.98 (MAX)
(24.89)
0.100 (TYP)
(2.54)
PIN 1 DENOTED BY
CONTRASTING
COLORED BEAD
0.78 (MAX)
(19.81)
0.018 ±0.002 DIA. PIN
(0.46 ±0.051)
(26 REQUIRED)
0.210 ±0.010
(5.33 ±0.25)
BOTTOM VIEW
1
26
0.700
(17.78)
0.600
(15.24)
0.200 (MAX)
(5.08)
PIN NUMBERS ARE
FOR REFERENCE ONLY
14
SIDE VIEW
8
21
TABLE 2. PINOUT (26 PIN)*
1 S1(S)
S1(R)
N.C.
26 +REF
(+Reference Input)
2 S2(S)
S2(R)
+COS(D)
25 -REF
(-Reference Input)
3 S3(S)
S3(R)
+SIN(D)
24 Analog Ground
4 N.C.
S4(R)
N.C.
23 EM
(Enable MSBs)
5 A (Resolution Control)**
22 E
(DC Error Output)
6 Digital Ground
21 VEL
(Velocity Output)
7
-5 V (Power Supply)
20 INH
(Inhibit)
8
+5 V (Power Supply)
19 EL
(Enable LSBs)
9
Bit 1 (MSB)
/Bit 9
18 BIT
(Built-In-Test)
10 Bit 2
/Bit 10
17 CB
(Converter Busy)
11 Bit 3
/Bit 11
16 Bit 8
/Bit 16**
12 Bit 4
/Bit 12
15 Bit 7
/Bit 15**
13 Bit 5
/Bit 13
14 Bit 6
/Bit 14
FIGURE 3. INHIBIT TIMING
FIGURE 4. ENABLE TIMING
FIGURE 5. SDC-14570/75 MECHANICAL OUTLINE
* Note: (S) = Synchro; (R) = Resolver; (D) = 2 V Resolver Direct
** Note: SDC-14575 Series only
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