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參數(shù)資料
| 型號： | SDC-14580-534S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | DDIP-36 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大小： | 202K |
| 代理商： | SDC-14580-534S |
10
Data Device Corporation
www.ddc-web.com
SDC-14580
H-05/04-0
change until CB returns to logic 0; if INH is applied during CB,
the latch will not lock until the CB pulse is over. The purpose of
the 50 ns delay is to prevent a race condition between CB and
INH where the up-down counter begins to change as an INH is
applied.
An INH input, regardless of its duration, does not affect the con-
verter update. A simple method of interfacing to a computer
asynchronous to CB is: (1) Apply lNH; (2) Wait 0.5 s min; (3)
Transfer the data; (4) Release INH.
A logic 1 for the lNH enables the output data to be updated. The
time it takes for INH to go to a logic 1 should be 100 ns minimum
before valid data is transferred. To allow the update of the output
data with valid information the INH must remain at a logic 1 for 1
s minimum (see FIGURE 12).
DATA TRANSFERS
Digital output data from the SDC-14580 can be transferred to 8-
bit and 16-bit bus systems. For 8-bit systems, the MSB and LSB
bytes are transferred sequentially. For 16-bit systems all bits are
transferred at the same time.
Data Transfer To 8-Bit Bus
FIGURES 13 and 14 show the connections and timing for trans-
ferring data from the SDC-14580 to an 8-bit bus.
As can be seen by the timing diagram the following occurs:
1. The converter INH control is applied and must remain low for
a minimum of 500 ns before valid data is transferred.
2. EM is set to a low state (logic 0) 150 ns MIN after INH goes
low and must remain low for a minimum of 150 ns before the
MSB data (1-8) is valid and transferred.
3. As EM is set to a high state (logic 1), EL is brought low for 150
ns MIN before the LSB data is valid and transferred.
4. EL should go high (to logic 1) at least 100 ns MAX before
another device uses the bus.
5. INH goes high and data transfer is done and the data refresh
cycle can begin. Note the time it takes for INH to go to a logic
1 should be 100 ns minimum before valid data is transferred.
Note: For further understanding refer to the beginning of this section (i.e., Digital
Interface, Digital Angle Outputs, Digital Angle Output Timing, and Inhibit).
16-Bit Data Transfer
Data transfer to the 16-bit bus is much simpler than the 8-bit bus.
FIGURES 15 and 16 show the connections and timing for trans-
ferring data from the SDC-14580 to a 16-bit bus.
As can be seen by the timing diagram (FIGURE 16) the follow-
ing occurs:
1. The converter INH control is applied and must remain low for
a minimum of 500 ns before valid data is transferred.
2. EM and EL are set to a low state (logic 0) 150 ns MIN after
INH goes low and must remain low for a minimum of 150 ns
before the data (1-16) is valid and transferred.
3. EM and EL should go high (to logic 1) at least 100 ns MAX
before another device uses the bus.
4. INH goes high and data transfer is done and the data refresh
cycle can begin. Note the time it takes for INH to go to a logic
1 should be 100 ns minimum before valid data is transferred.
Note: For further understanding refer to the beginning of this section (i.e., Digital
Interface, Digital Angle Outputs, Digital Angle Output Timing, and Inhibit).
INTERFACING - ANALOG OUTPUTS
The analog outputs are AC error (e), Internal DC Reference
Voltage, and Velocity (VEL).
AC ERROR (e, PIN 27)
AC Error Out (e) is used in CT mode. The AC error is propor-
tional to the difference between the input angle
θ and the digital
input angle
φ, (θ - φ), with a scaling of:
50 mV rms/LSB (10-bit mode)
25 mV rms/LSB (12-bit mode)
12.5 mV rms/LSB (14-bit mode)
6.3 mV rms/LSB (16-bit mode)
TABLE 5. VELOCITY CHARACTERISTICS
PARAMETER
UNITS
TYP
MAX
Polarity
Output Voltage
Voltage Scaling
Scale Factor
Scale Factor TC
Reversal Error
Reversal Error TC
Linearity
Linearity TC
Zero Offset
Zero Offset TC
Load
V
RPS/V
%
PPM/°C
%
PPM/°C
% output
PPM/°C
mV
V/°C
kOhms
±13
5
100
1
25
1
25
15
25
—
±10 min
10
200
2
50
2
50
40
50
3 min
TABLE 6. VOLTAGE SCALING RESOLUTION
(VALUES IN RPS/VOLT)
10 BIT
12 BIT
14 BIT
16 BIT
80
20
5
1.25
Note: If the resolution is changed while the input is changing, then the
velocity output voltage and the digital output will have a transient
until it settles to the new velocity scaling at a speed determined
by the bandwidth. If additional information is required, consult
the factory.
Positive for increasing angle
See voltage scaling TABLE 6
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| SDC-14580-534Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14580-535L | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14580-535Q | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| SDC-14580-535S | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
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