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參數(shù)資料
| 型號： | SDC-14585-392 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | DDIP-36 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 202K |
| 代理商： | SDC-14585-392 |
9
Data Device Corporation
www.ddc-web.com
SDC-14580
H-05/04-0
The second byte will contain either bits 9-10 (10-bit resolution),
bits 9-12 (12-bit resolution), bits 9-14 (14-bit resolution), or bits
9-16 (16-bit resolution). All unused LSBs will be at logic 0. TABLE
4 lists the angular weight for the digital angle outputs.
The digital angle outputs are valid 150 ns after EM or EL are acti-
vated with a logic 0 and are high impedance within 100 ns, max
after EM and EL are set to logic 1 (see FIGURE 9). Both enables
are internally pulled up to +5 V // 5 pf max current sources.
DIGITAL ANGLE OUTPUT TIMING
The digital angle outputs 10, 12, 14, or 16 parallel data bits and
CONVERTER BUSY (CB). All logic outputs are short-circuit
proof to ground and +5 V. The CB output is a positive, 0.4 to 1.0
s pulse.
The digital output data changes approximately 50 ns after the
leading edge of the CB pulse because of an internal delay. Data
is valid 0.2 s after the leading edge of CB (see FIGURE 10).
The angle is determined by the sum of the bits at logic 1. The dig-
ital outputs are valid 150 ns max after EM or EL go low and are
high impedance within 100 ns max of EM or EL going high.
INHIBIT (INH, PIN 33)
When an Inhibit (INH) input is applied to the SDC-14580, the
Output Transparent Latch is locked causing the output data
bits to remain stable while data is being transferred. (See
FIGURE 11.) The output data bits are stable 0.5 s after INH
goes to logic 0.
A logic 0 at the T input of the Inhibit Transparent Latch latches
the data, and a logic 1 applied to T allows the bits to change. This
latch also prevents the transmission of invalid data when there is
an overlap between CB and INH. While the counter is not being
updated, CB is at logic 0 and the INH latch is transparent; when
CB goes to logic 1, the INH latch is locked. If CB occurs after INH
has been applied, the latch will remain locked and its data will not
FIGURE 12. OUTPUT DATA UPDATE TIMING
;;
DATA
0 - 1 s
INH
100 ns MIN
2 s MIN
UPDATE
STABLE
FIGURE 11. INHIBIT TIMING DIAGRAM
DATA
VALID
0.5 s
ASYNCHRONOUS TO CB
INH
FIGURE 10. CONVERTER BUSY TIMING DIAGRAM
;;
DATA
0.4 - 1.0 s MIN
CB
0.2 s MIN
1.5 s MIN
DEPENDS ON d
φ/dt
VALID
TABLE 4. DIGITAL ANGLE OUTPUTS
BIT
DEG/BIT
MIN/BIT
1 (MSB ALL MODES)
2
3
4
5
6
7
8
9
10 (LSB 10 BIT MODE)
11
12 (LSB 12 BIT MODE)
13
14 (LSB 14 BIT MODE)
15
16 (LSB 16 BIT MODE)
180
90
45
22.5
11.25
5.625
2.8125
1.4063
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
31.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: EM enables the 8 MSBs and EL enables the LSBs.
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