參數(shù)資料
型號: SDC-19204-302
廠商: DATA DEVICE CORP
元件分類: 位置變換器
英文描述: SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP40
封裝: 1.140 X 2.020 INCH, 0.230 INCH HEIGHT, TDIP-40
文件頁數(shù): 9/16頁
文件大小: 124K
代理商: SDC-19204-302
2
TABLE 1. SDC-19204/6 SPECIFICATIONS
These specifications apply over temperature range, power supply range and reference frequency amplitude range; ±10% signal amplitude variation
and up to 10% harmonic distortion in the reference.
PARAMETER
VALUE
DESCRIPTION
RESOLUTION
10, 12, 14, or 16 bits
Programmable.
ACCURACY GRADES
8, 4, 3, or 2 minutes
Max + 1 LSB of selected resolution (see Ordering Information).
DIFFERENTIAL LINEARITY
16, 12, 8, or 4
LSBs in the 16th bit (see Ordering Information).
REPEATABILITY
1 LSB max
REF INPUT CHARACTERISTICS
Voltage Range
Single-Ended Input Impedance
Frequency Range
4-130 V rms
100k Ohm min; 110k Ohm nom
47 Hz to 1 kHz
See TABLE 4., Dynamic Characteristics.
SIGNAL INPUT CHARACTERISTICS
Synchro
Zin Line to Line
Zin Each Line to Ground
Common Mode Range
11.8 V L-L
90 V L-L
52k Ohm
123k Ohm
70k Ohm
180k Ohm
25 V max
180 V max
Voltage options and minimum input impedance balanced.
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Max Voltage w/o Damage
Loading
INH (Inhibit)
EM (Enable bits 1-8)
EL (Enable bits 9-16)
S (Control Transformer)
BW (Bandwidth)
Resolution Control
10 Bit
12 Bit
14 Bit
16 Bit
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
-0.3 to 11 V
-10
A max
TTL/CMOS compatible.
Pull-up current source to + 5 V//5 pf max CMOS transient protected.
Logic 0 inhibits Logic 1 enables Data stable within 0.3
s.
Logic 0 enables data valid within 150 ns Logic 1 high Z within 100 ns.
Logic 0 for Control Transformer, Logic 1 for normal tracking.
Logic 1 = High BW (53 Hz); Logic 0 = Low BW (13 Hz).
B (pin#8)
A (pin#7)
00
01
10
11
Unused output bits are at logic 0.
OUTPUTS
Parallel Data
CB (Converter Busy)
U (Direction)
MC (Major Carry)
BIT (Built-in-Test)
LOS (Loss of Signal)
Drive Capability
10, 12, 14, or 16 bits
Logic 0:1 TTL Load
Logic 1:10 TTL Loads
High Z:10
A/5 pf max
Natural binary angle positive logic.
0.4
s to 0.7 s positive pulse; leading edge initiates counter update.
Logic 1 counts up Logic 0 counts down.
Logic 0 at MC.
Logic 0 for BIT condition.
Logic 1 for LOS (1-3
A pull-up to +5 V).
-1.6 mA at 0.4 V max.
0.4 mA at 2.8 V min.
ANALOG OUTPUTS
V (Internal DC ref)
VEL (Velocity)
e (AC error)
Dynamic Characteristics
+5.5 V nom
50 mV rms per LSB of error
25 mV rms per LSB of error
12.5 mV rms per LSB of error
6.3 mV rms per LSB of error
See TABLE 5 - Velocity Characteristics.
10-bit mode.
12-bit mode.
14-bit mode.
16-bit mode.
See TABLE 4 Dynamic Characteristics.
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