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參數(shù)資料
| 型號(hào)： | SDC-361-L-3 |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP32 |
| 封裝： | 3.125 X 2.625 INCH, 0.820 INCH HEIGHT, PACKAGE-54/32 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 102K |
| 代理商： | SDC-361-L-3 |
3
To prevent damage to the input transformers, the maximum volt-
age should not exceed the specified input voltage by more than
30%. The maximum common mode voltage (DC plus recurrent
AC peak) should not exceed 500 V.
DIGITAL INPUTS
Logic inputs are low power Schottky and the can drive remote
loads. The BIT logic output is a built-in-test derived from the
crossover detector. It goes to logic 1 whenever the digital output
is not tracking the input signal within the range of the fine speed
synchro or resolver.
TIMING
Whenever an input signal change occurs, the converter changes
the digital angle in steps of 1 LSB, and generates a converter
busy pulse (CB). The output data change is initiated at the lead-
ing edge of the CB pulse, and the output is stable within 0.2 sec
after the leading edge. Extra CB pulses will not occur if the input
angle changes while the counter is locked by the INH. The sim-
plest method of interfacing with a computer is to transfer data at
a fixed time interval after the inhibit is applied. The converter will
ignore an inhibit applied during the “busy” interval until that inter-
val is over. Timing is as follows: (a) apply the inhibit, (b) wait 0.2
sec, (c) transfer the data and (d) release the inhibit.
ANALOG VELOCITY OUTPUT
VEL is a DC voltage proportional to the angular velocity d
θ/dt =
d
φ/dt. The output is derived from an op-amp with low output
impedance and is short-circuit protected. Other characteristics
are listed in TABLE 1.
DYNAMIC PERFORMANCE
A Type II servo loop (Kv =
∞) and very large acceleration con-
stants give these converters superior dynamic performance, as
listed in TABLE 1. If the power supply voltages are not the ±15
VDC nominal values, the specified input rates for full accuracy
will increase or decrease in proportion to the fractional change in
voltage. The +15 V supply voltage will determine the maximum
positive velocity. The -15 V supply voltage will determine the
maximum negative velocity.
As long as the maximum tracking rate is not exceeded, there will
be no lag in the converter output. If a step input occurs, as is
likely when the power is initially turned on, the response will be
critically damped. After initial slewing at the maximum tracking
rate of the converter, there is one overshoot which is inherent to
a Type II servo. The overshoot settling to final value is a function
of the small signal settling time.
The loop dynamics of DDC’s tracking S/D converters are
described by the unity feedback configuration shown.
The
closed-loop transient response is nominally critically damped,
and all loop dynamics can be determined from the diagram and
formulas given.
G
1
+
e
–
UNITY FEEDBACK
FIGURE 4. S/D CONVERTER LOOP DYNAMICS
DIGITAL
OUTPUT
ANGLE
INPUT
At 60 Hz
At 400 Hz
G =
S
33
+ 1)
662 (
S
330
+ 1)
S2 (
S
133
+ 1)
2662 (
S
1330
+ 1)
S2 (
CONVERTER
BUSY (CB)
INHIBIT
(INH)
DATA
VALID
TABLE 2. TIMING DIAGRAM
5.5 sec MIN
DEPENDS ON d
θ/dt
1-2.5 sec
0.2 sec
VALID
“ 1 “
“ 0 “
“ 1 “
“ 0 “
OVERSHOOT
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
θ2
θ1
FIGURE 3. STEP RESPONSE INPUT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
180
90
45
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10,800
5,400
2,700
1,350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
.66
.33
TABLE 2. BIT WEIGHT
BIT
DEG/BIT
MIN/BIT
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