參數(shù)資料
型號: SDM872J
英文描述: 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS
中文描述: 16單端/ 8差分輸入12位數(shù)據(jù)采集系統(tǒng)
文件頁數(shù): 9/27頁
文件大?。?/td> 256K
代理商: SDM872J
SDM862/863/872/873
9
Matching of R
1
and R
3
is required to maintain high
common-mode rejection (CMR), R
2
sets the gain and may
be varied without effect on CMR.
To ensure that the effects of temperature are minimized
when altering the gain with external components, it is very
important to use low tempco resistors. When connecting the
output sense, ensure that series resistance is minimized
because resistance present will degrade CMR.
FIGURE 5. Increasing Output Amplifier Gain.
20k
20k
4.44k
404
FET Input
10k
10k
10k
10k
FET Input
A1
A3
A2
R
1
R
2
R
3
FIGURE 4. Use External Gain Set Resistor.
+
+
+
+
C
f
+
R
f
MUX
C
M
–V
+V
C
f
C
f
R
f
C
f
R
f
C
f
10V
10V
R
f
R
i
R
f
R
f
FIGURE 3. Example Application Illustrating Flexible Signal
Conditioning.
Output
20k
20k
X10
X100
4.44k
404
FET Input
10k
10k
10k
10k
FET Input
+In
R
G
R
EXT
–In
A1
A3
A2
Sense
Ref
Where it is necessary to keep the input amplifiers from
saturating or increasing the overall gain, then the gain of the
output amplifier can be increased from unity by using the
circuit in Figure 5.
The values of the resistors in Figure 5 are in the following
table.
O/P GAIN
R
1
and R
3
R
2
2
5
1200
1000
1500
2740
511
340
10
FIGURE 6. Typical INA Settling Time and CMR.
10
100
1
1k
10k
100k
1M
120
100
80
60
40
20
0
C
Frequency (Hz)
Gain (V/V)
S
1
10
100
10
5
0
CMR vs FREQUENCY
SETTLING TIME vs GAIN
(0.01%, 20V Step)
Gain = 1
Gain = 10
Gain = 100
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