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參數(shù)資料
| 型號(hào)： | SDM872R |
| 英文描述： | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| 中文描述： | 16單端/ 8差分輸入12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 256K |
| 代理商： | SDM872R |
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SDM862/863/872/873
21
mentation amplifier is settling to a new analog value while
the ADC is still carrying out the previous conversion.
The digital supply voltage is +5V and is also LC-filtered.
All supply lines are bypassed with a 10
μ
F tantalum and a
100nF ceramic capacitor situated
as close as possible
to the
package.
If the voltage regulators for the
±
15V are not used, small
inductors for decoupling of the supply voltages are recom-
mended. If inductors are not fitted a dynamic ground loop
will be created from supply lines via bypass capacitors to
analog common.
INPUT PROTECTION
The multiplexer is protected up to an input voltage which
can exceed the supply voltage by a maximum of 20V. This
means, that with
±
15V supply voltage, the input voltage can
be
±
35V without damage. This is also the case when the
supply voltages are switched off (0V). The maximum input
voltage can then be
±
20V. For higher overvoltage protection
a series resistor has to be used. The current via the multi-
plexer should be limited to 20mA absolute maximum, 1mA
is preferred. For example, a 10k
series resistor would give
an additional 10V overprotection.
For much higher overvoltages (e.g. 100V), high value series
resistors cannot be used as offset errors would result. In
practice, a combination of series resistors and diodes is used.
The diodes are connected to
±
15V and will conduct when-
ever the input voltage exceeds the
±
15V supply voltage. The
diodes are selected by signal source impedance, as well as
filter resistance, as the diode leakage current across the
series resistor can cause offset and linearity errors. In this
circuit, IN4148 together with 10k
are used.
INPUT FILTER
Processor noise can be induced in the analog ground. Input
filtering is therefore recommended for analog data acquisi-
tion. Such high frequency noise signals can cause dynamic
overload of the instrumentation amplifier resulting in non-
linear behavior. This leads directly to digitizing errors.
The design of the filter takes into account the characteristics
of the SDM and of the signal source.
The following points have to be considered:
—The stray capacitance, output capacitance of the multi-
plexer and input capacitance of the instrument amplifier
(up to 80pf in some cases) has to be discharged in order
to minimize errors caused by ‘charge sharing.’
—The series resistor limits the current in the protection
diodes, but it also has to be selected for the required filter
time constant.
—The noise rejection of the filter has to be >80db in order
to satisfy a 12-bit A/D conversion.
As well as considering the above, different calculations
have to be carried out for single and differential input
signals.
Single-Ended Measurement
R
f
limits the maximum input current through the protection
diodes. In this case, R
f
has been chosen as 10k
and
together with the capacitor C
g
, forms the input filter time
constant (C
g
= 0.47
μ
F). The time constant must be chosen
according to the requirements of the input signal bandwidth
and noise rejection. The multiplexer capacitance (C
m
) is
discharged mainly by C
g
. This means C
g
has to be suffi-
ciently large compared with C
m
or charged via R
f
prior to re-
sampling of the signal.
FIGURE 26.
INA
Analog In
R
f
Mux
C
m
C
g
FIGURE 27.
INA
C
g
Mux
C
m
C
f
R
f
R
f
Analog In
Analog In
C
g
Differential Measurement
Capacitor C
f
, is used for limiting the input signal frequency.
The bandwidth is calculated as follows:
1
4
π
f
C
f
When selecting the value of C
f
, it should be noted that C
m
has to be discharged when switching the multiplexer chan-
nels. This means that the voltage error of C
f
(induced by
‘charge sharing’ with C
m
) has to be smaller than 1LSB.
Therefore, C
f
should have a minimum value of a 0.47
μ
F.
The resistors R
f
, together with the source impedance, have to
be sufficiently small in order to recharge C
f
prior to signal
sampling. This prevents errors in the signal value caused by
the charge stored on C
m
by the previously selected channel.
The 2 capacitors C
g
form together with R
f
a common-mode
filter. This filter greatly improves accuracy in a noisy envi-
ronment (decrease of common-mode rejection of instrumen-
tation amplifier with increasing frequency).
For good common-mode filter operation, both time con-
stants R
f
and C
g
should match each other within 2%. Addi-
tional errors will be induced by a mismatch.
Selected values are: C
f
= 0.47
μ
F, C
g
= 10nF, R
f
= 10k
. The
filter reduces the signal slew rate so that the instrumentation
amplifier can follow the voltage variation of the signal with
the noise component eliminated.
In general, all measurements which require more than a gain
of 10 should be done in differential mode. Single ended
F
f
=
R
f
> > C
g
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SDM872S | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873 | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873A | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873B | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873J | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDM872S | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873 | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873A | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873B | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873J | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
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