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參數(shù)資料
| 型號： | SDM872S |
| 英文描述： | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| 中文描述： | 16單端/ 8差分輸入12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 256K |
| 代理商： | SDM872S |
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SDM862/863/872/873
18
CONTROLLING THE SDM
The Burr-Brown SDM family can be easily interfaced to
most microprocessor systems, as shown in Figures 17-20.
The microprocessor may control each conversion, or the
converter may operate in a stand-alone mode controlled only
by the R/C input.
STAND-ALONE OPERATION
The stand-alone mode is used in systems containing dedi-
cated input ports which do not require full bus interface
capability.
Control of the converter is accomplished by a single control
line connected to R/C. In this mode CS and BYTE SELECT
are connected to LOW and CE and DATA MODE are
connected to HIGH. The output data are presented as 12-bit
words.
Conversion is initiated by a High-to-Low transition of R/C.
The three-state data output buffers are enabled when R/C is
high and STATUS is low. Thus, there are two possible
modes of operation; conversion can be initiated with either
positive or negative pulses. In each case the R/C pulse must
remain low for a minimum of 50ns.
Figure 21 illustrates timing when conversion is initiated by
an R/C pulse which goes low and returns to the high state
during the conversion. In this case, the three-state outputs go
to the high-impedance state in response to the falling edge of
R/C and are enabled for external access of the data after
completion of the conversion. Figure 22 illustrates the tim-
ing when conversion is initiated by a positive R/C pulse. In
this mode the output data from the previous conversion is
enabled during the positive portion of R/C. A new conver-
sion is started on the falling edge of R/C, and the three-state
outputs return to the high impedance state until the next
occurrence of a high R/C pulse. Table I lists timing specifi-
cations for stand-alone operation.
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the BYTE SELECT input, which is latched upon receipt
of a conversion start transition. BYTE SELECT is latched
because it is also involved in enabling the output buffers. No
other control inputs are latched. If BYTE SELECT is latched
high, the conversion continues for 8 bits. The full 12-bit
conversion will occur if BYTE SELECT is low. If all 12 bits
are read following an 8-bit conversion, the 3LSBs (DB0-
DB2) will be low (logic 0) and DB3 will be high (logic 1).
Word 1
Word 2
Processor
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDM
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
FIGURE 23. 12-Bit Data Format for 8-Bit Systems (connected as Figures 18 and 19).
Conversion Start
A conversion is initiated by a transition on any of three logic
inputs (CE, CS, and R/C)—refer to Figure 9. The last of the
three to reach the required state start the conversion and thus
all three may be dynamically controlled. If necessary, they
may change state simultaneously, and the nominal delay
time is independent of which input actually starts the con-
version. If it is desired that a particular input establish the
actual start of conversion, the other two should be stable a
minimum of 50ns prior to the transition of that input. Timing
relationships for start of conversion timing are illustrated in
Conversion Cycle Timing of the Digital Specifications.
SYMBOL
PARAMETER
MIN
TYP
MAX UNITS
t
HRL
t
DS
t
HDR
t
HS
t
HS
87X
t
HRH
t
DDR
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
STS Delay After Data Valid
50
ns
ns
ns
ns
ns
ns
ns
200
25
300
100
150
500
300
1000
600
High R/C Pulse Width
Data Access Time
150
FIGURE 22. R/C Pulse High—Outputs Enabled Only Where
R/C is High.
R/C
Status
DB11–
DB0
Data Valid
High-Z State
t
HRH
t
DS
t
High-Z
t
C
t
HDR
FIGURE 21. R/C Pulse Low—Outputs Enabled After Con-
version.
R/C
Status
DB11–DB0
Data Valid
Data Valid
High-Z State
t
HRL
t
DS
t
HDR
t
HS
t
C
TABLE I. Stand-Alone Mode Timing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SDM873 | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873A | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873B | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873J | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873K | 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDM873 | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873A | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873B | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873J | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
| SDM873K | 制造商:BB 制造商全稱:BB 功能描述:16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS |
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