參數(shù)資料
型號(hào): SE370C732Ayyz
廠商: Texas Instruments, Inc.
英文描述: TMS370 MICROCONTROLLER FAMILY DATA BOOK
中文描述: TMS370微控制器系列數(shù)據(jù)手冊(cè)
文件頁數(shù): 32/78頁
文件大?。?/td> 919K
代理商: SE370C732AYYZ
TIMING CONVENTIONS
1–24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
hold time
The time interval during which a signal is retained at a specified input terminal after an active transition occurs
at another specified input terminal.
NOTES:
1. The hold time is the actual time interval between two signal events and is determined by the system in which the digital circuit
operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is assured.
2. The hold time can have a negative value in which case the minimum limit defines the longest interval (between the release
of the signal and the active transition) for which correct operation of the digital circuit is assured.
Example symbology:
Classified
t
h(EH-A)
Description
Hold time, address, R/W and OCF from EDS, CSE1, CSE2, CSH1, CSH2,
CSH3, and CSPF high
Hold time, write data time from EDS high
Hold time, read time from EDS high
Hold time, WAIT time from SYSCLK high
Hold time, analog input from start of conversion
t
h(EH-D)W
t
h(EH-D)R
t
h(SCH-WT)
t
h(AN)
NOTE: The from-to sequence in the order of subscripts in the unclassified form is maintained in the classified form. In the case of hold times,
this causes the order to seem reversed from what would be suggested by the terms.
pulse duration (width)
The time interval between the specified reference points on the leading and trailing edges of the pulse
waveform.
Example symbology:
Classified
t
w(CI)
t
w(PGM)B
t
w(PGM)AR
t
w(EPGM)
t
w(SCL)
t
w(SCH)
t
w(SCCL)
t
w(SCCH)
t
w(SPCL)
t
w(SPCH)
t
w(S)
t
w
Description
Pulse duration, XTAL2/CLKIN
Pulse duration, programming signal to ensure valid data is stored (byte mode)
Pulse duration, programming signal to ensure valid data is stored (array mode)
Pulse duration, programming signal
Pulse duration, SYSCLK low
Pulse duration, SYSCLK high
Pulse duration, SCICLK low
Pulse duration, SCICLK high
Pulse duration, SPICLK low
Pulse duration, SPICLK high
Pulse duration, sample time per kilohm of source impedance
Pulse duration, EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low
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