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參數(shù)資料
| 型號： | SHC702 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-Bit 512kHz Sampling A/D Converter System(16位 512k赫茲采樣頻率的A/D轉(zhuǎn)換系統(tǒng)) |
| 中文描述： | 16位512kHz采樣A / D轉(zhuǎn)換器系統(tǒng)（16位為512k赫茲采樣頻率的的A / D轉(zhuǎn)換系統(tǒng)） |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 164K |
| 代理商： | SHC702 |
ADC701/SHC702
13
FFT Parameters
Accurate FFT analysis of 16-bit systems requires adequate
computing hardware and software. The FFT length (number
of points) should be relatively large—at least 4K and prefer-
ably 16K or larger. There are several reasons for this:
1. The converter itself has 64K codes. Ideally, the test
would guarantee that all codes are tested at least once.
Practically speaking, however, that would require im-
mensely long FFTs (>>64K points) or averaging of a
large number of smaller FFTs. By using an FFT length of
4K or greater and proper selection of the test frequencies,
a very good statistical picture of the ADC performance
will be obtained which shows the effect of any defects in
the transfer function.
2. The noise floor of the output spectrum is not low enough
if less than 4K points are taken. Shorter FFTs have fewer
bins to cover the output spectrum, so a larger fraction of
the total system noise appears in each bin. Although the
SNR of the ADC701/SCH702 system is in the range of
–93dB, the noise level of the available generators may
increase the total measured noise power to –80dB. Every
doubling of the FFT length will spread the noise power
among twice as many bins, resulting in a 3dB reduction
of the spectral noise floor. In order to resolve spurious
components that are at the level of –110dB, an average
noise floor of less than –113dB would be barely ad-
equate. This requires at least 2048 bins in the output
half-spectrum, corresponding to a 4K-point FFT. Even
at this level, it will be difficult or impossible to separate
higher order harmonics in the ADC701 response from
the average noise level, indicating that longer FFTs are
desirable.
3. Following the guidelines for test frequency selection
which are outlined in the next section, it becomes clear
that longer FFTs allow a much wider choice of test
frequencies without concern for sophisticated data win-
dowing or code coverage problems.
Besides the consideration of FFT length, it is important to
realize that the FFT calculations must be performed with
high-precision arithmetic. The use of 32-bit fixed or floating
point calculations will generally be inadequate because the
noise floor due to calculation errors alone will interfere with
the ADC performance data. Unfortunately, this considera-
tion precludes the use of most DSP accelerator boards and
similar hardware. In order to preserve the full dynamic range
of the ADC output, it is best to use standard 64- or 80-bit
arithmetic. To avoid excessively long calculation times, the
FFT algorithm should be written in an efficiently compiled
language and make use of techniques such as trigonometric
look-up tables in software and dedicated floating-point
coprocessors in hardware. There are several commercial
software packages available from Burr-Brown and others
that meet these requirements.
SELECTION OF TEST FREQUENCIES
The FFT (and any similar DSP operation) treats the total
time-domain record length as one cycle of an infinitely long
periodic signal. Therefore, if the end of the sampled record
does not match up smoothly with the beginning, the output
spectrum will contain serious errors known as leakage or
truncation error
(2)
. This well-known problem is usually
handled by applying a windowing function to the time-
domain samples, suppressing the worst effects of the mis-
match. However, the most often used windows such as
Hanning, Hamming, raised cosine, etc., are completely inad-
equate for 16-bit ADC testing. More sophisticated functions
such as the four-sample Blackman-Harris window
(3)
will
provide much better results, although there still will be
obvious spreading of the spectral lines.
The most successful approach is to eliminate the need for
windowing by properly selecting the test signal frequency
(or frequencies) in relation to the ADC sampling frequency
(4)
.
If the time sample contains exactly an integer number of
cycles, then there is no mismatch or truncation error. An-
other point to consider is that the sampling frequency should
not be an exact integer multiple of the signal frequency,
which would tend to reduce the number of different ADC
codes that are tested and also tend to artificially concentrate
quantization error in the harmonics of the test signal.
Both of these criteria are met by choosing an FFT length
which is a power of two (the most standard and fastest to
compute) and choosing a test frequency which causes an
exact
odd
integer number of cycles to appear in the time
record. In software, this selection can be accomplished very
easily:
1. Determine the desired sampling frequency f
S
.
2. Determine the desired input signal frequency f
APPROX.
3. Determine the FFT length N, which should be a power of
2 (e.g., 4096 or 16384).
4. Divide f
APPROX
by f
S
, multiply the quotient by N, and
round the result to the nearest odd integer. This is M, the
number of cycles in the time record.
5. Multiply M by f
S
and divide by N to obtain the exact
input signal frequency f
ACTUAL
.
SIGNAL GENERATOR CONSIDERATIONS
To suppress leakage effects, the calculated ratio of f
S
to
f
ACTUAL
must be precisely maintained during the test. This
requirement is met easily by the use of synthesized signal
generators whose reference oscillators can be locked to-
gether. Other possible approaches include external phase
locking of non-synthesized generators and direct digital
synthesis techniques. If it is not possible to use phase-locked
signals, then a Blackman-Harris window may be used as
mentioned previously.
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