參數(shù)資料
型號: SI3056DC1-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/94頁
文件大?。?/td> 0K
描述: DAUGHTERCARD DAA SI3056/SI3019
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,數(shù)據(jù)采集裝置(DAA)
已用 IC / 零件: Si3056
已供物品: 板,CD
Si3056
Si3018/19/10
14
Rev. 1.05
Figure 6. Serial Interface Timing Diagram (Slave Mode, DCE = 1, FSD = 1)
Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = 1)
(VA = Charge Pump, VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL =20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Cycle Time, MCLK
tc
244
1/256 Fs
ns
Setup Time, FSYNC
↑ before MCLK↓*tsu1
——
20
ns
Delay Time, FSYNC
↑ after MCLK↓*td1
——
20
ns
Setup Time, SDI before MCLK
tsu3
——
20
ns
Hold Time, SDI After MCLK
th2
——
20
ns
Delay Time, MCLK
↑ to SDO
td3
——
20
ns
Delay Time, MCLK
↑ to FSYNC↑
td1
——
20
ns
Delay Time, MCLK
↑ to FSYNC↓
td2
——
20
ns
*Note:
Tsu1 and Th1 are listed for applications where the controller drives the MCLK and FSYNC instead of a master DAA.
MCLK
FSYNC
(mode 1)
t
d1
t
SU1
t
d1
t
h1
t
C
t
d2
FSYNC
(mode 0)
SDI
SDO
D15
D0
t
h2
t
su3
t
d3
D15
D0
D14
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