參數資料
型號: SI3056SSI2-EVB
廠商: Silicon Laboratories Inc
文件頁數: 59/94頁
文件大?。?/td> 0K
描述: BOARD EVAL SI3056/SI3010 SSI
標準包裝: 1
主要目的: 電信,數據采集裝置(DAA)
已用 IC / 零件: Si3056
已供物品: 板,CD
Si3056
Si3018/19/10
62
Rev. 1.05
Reset settings = 0000_0000
Register 18. International Control 3
Bit
D7
D6D5D4D3D2D1
D0
Name
RFWE
Type
R/W
Bit
Name
Function
7:2
Reserved Read returns zero or one.
1RFWE
Ring Detector Full-Wave Rectifier Enable.
When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the asser-
tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow
the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect
one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter time-
out of approximately five seconds.
RNGV
RFWE
RGDT
00
Half-Wave
0
1
Full-Wave
1
0
Validated Ring Envelope
1
Ring Threshold Crossing One-Shot
0
Reserved Read returns zero or one.
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