參數(shù)資料
型號: SI3216MDCQX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/122頁
文件大小: 0K
描述: DAUGHTER CARD W/DISCRETE INTRFC
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3216
已供物品: 板,CD
Si3216
110
Rev. 1.0
Not
Recommended
fo
r N
ew
D
esi
gn
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5. Pin Descriptions: Si3216
Pin #
QFN
Pin #
TSSOP
Name
Description
35
1
CS
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high-impedance.
When active, the serial port is operational.
36
2
INT
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
37
3
PCLK
PCM Bus Clock.
Clock input for PCM bus timing.
38
4
DRX
Receive PCM Data.
Input data from PCM bus.
15
DTX
Transmit PCM Data.
Output data to PCM bus.
2
6
FSYNC
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse for-
mat.
3
7
RESET
Reset.
Active low input. Hardware reset used to place all control registers in the default
state.
4
8
SDCH
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
TSSOP
27
28
29
30
31
34
33
32
CS
INT
PCLK
DTX
FSYNC
RESET
SDCH
SCLK
SDI
SDITHRU
SDO
DCFF
DCDRV
GNDD
TEST
DRX
1
2
3
4
5
6
7
8
9
10
11
12
13
26
25
14
SDCL
VDDA1
IREF
CAPP
ITIPN
VDDD
VDDA2
ITIPP
35
36
37
38
QGND
CAPM
IRINGP
IRINGN
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
IGMP
GNDA
IGMN
SRINGAC
STIPAC
15
16
17
18
19
24
23
22
21
20
27
28
29
30
31
34 33 32
1
2
3
4
5
6
7
8
9
10
11
12 13
26
25
14
35
36
37
38
15 16 17 18 19
24
23
22
21
20
QFN
DTX
FSYNC
RESET
SDCH
SDCL
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIP
E
SV
BA
T
SRING
E
ST
IP
AC
SRINGA
C
IGMN
G
NDA
IGMP
IRINGN
IRINGP
VDDA2
ITIPP
ITIPN
VDDD
GNDD
TEST
DCFF
DCDRV
SDITHRU
SDO
SDI
SCL
K
CS
INT
PCL
K
DR
X
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