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參數(shù)資料
| 型號： | Si3232 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING |
| 中文描述： | 兩個可編程的CMOS用戶接口與在線監(jiān)測 |
| 文件頁數(shù)： | 37/128頁 |
| 文件大小： | 2327K |
| 代理商： | SI3232 |
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Si3232
Preliminary Rev. 0.96
37
4.6. Ringing Generation
The Si3232 is designed to provide a balanced ringing
waveform with or without dc offset. The ringing
frequency, cadence, waveshape, and dc offset are all
register-programmable.
Using a balanced ringing scheme, the ringing signal is
applied to both the TIP and the RING lines using ringing
waveforms that are 180° out of phase with each other.
The resulting ringing signal seen across TIP-RING is
twice the amplitude of the ringing waveform on either
the TIP or the RING line, which allows the ringing
circuitry to withstand only half the total ringing amplitude
seen across TIP-RING.
Figure 16. Balanced Ringing Waveform and
Components
The purpose of an internal ringing scheme is to provide
>40 V
rms
into a 5 REN load at the terminal equipment
using a user-provided ringing battery supply. The
specific ringing supply voltage required depends on the
ringing voltage desired.
The ringing amplitude at the terminal equipment
depends on the loop impedance as well as the load
impedance in REN. The following equation can be used
to determine the TIP-RING ringing amplitude required
for a specific load and loop condition.
Figure 17. Simplified Loop Circuit During
Ringing
where
When ringing longer loop lengths, adding a dc offset
voltage is necessary to reliably detect a ring trip
condition (off-hook phone). Adding dc offset to the
ringing signal decreases the maximum possible ringing
amplitude. Adding significant dc offset also increases
the power dissipation in the Si3200 and may require
additional airflow or a modified PCB layout to maintain
acceptable operating temperatures. The Si3232
automatically applies and removes the ringing signal
during V
OC
-crossing periods to reduce noise and
crosstalk to adjacent lines. Table 23 provides a list of
registers required for internal ringing generation.
RING
TIP
V
RING
V
TIP
SLIC
V
OFF
GND
V
TIP
V
RING
V
BATH
V
PK
V
OV
V
CM
V
OFF
R
LOOP
V
RING
R
LOAD
V
TERM
+
–
R
OUT
V
TERM
V
RING
R
R
LOOP
R
LOAD
R
OUT
+
+
----------------------------------------------------------------
×
=
R
LOOP
0.09
per foot for 26 AWG wire
=
R
OUT
320
=
R
LOAD
#
REN
-------------------
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Si3200-KS | DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING |
| Si3200-X-FS | DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING |
| Si3200-X-GS | DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING |
| Si3232-X-FQ | DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING |
| Si3232-X-GQ | DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3232-BQ | 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-BQR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3232DC0-EVB | 功能描述:子卡和OEM板 Si3232 DAUGHTER CARD RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| SI3232DCX-EVB | 功能描述:子卡和OEM板 Si3232 DAUGHTER CARD RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| SI3232-FQ | 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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