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參數(shù)資料
| 型號： | SI5010-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR SI5010 |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘和數(shù)據(jù)恢復（CDR） |
| 已用 IC / 零件： | SI5010 |
| 已供物品： | 板 |
| 其它名稱： | 336-1121 |
Si5010
14
Rev. 1.4
5. Pin Descriptions: Si5010
Figure 10. Si5010 Pin Configuration
Table 8. Si5010 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1
REXT
External Bias Resistor.
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 k
Ω (1%) resis-
tor.
2, 7, 11, 14
VDD
2.5 V
Supply Voltage.
Nominally 2.5 V.
3, 8, 18, and
GND Pad
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 11)
must be connected directly to supply ground.
4
5
REFCLK+
REFCLK–
ISee Table 2
Differential Reference Clock.
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
6LOL
O
LVTTL
Loss-of-Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
9
10
DIN+
DIN–
ISee Table 2
Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins.
GND
Pad
Connection
15
14
13
12
11
PWRDN/CAL
DOUT+
VDD
DOUT–
VDD
1
2
3
4
5
VDD
GND
REFCLK–
REXT
REFCLK+
20
19
18
17
16
NC
RAT
ESEL
CL
KO
UT
–
CL
KO
UT
+
GND
6
7
8
9
10
LOL
GND
DIN+
DIN–
VDD
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