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參數(shù)資料
| 型號(hào)： | SI5100-G-BC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SERIAL/DESERIAL 195CBGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 195-BBGA |
| 供應(yīng)商設(shè)備封裝： | 195-BGA（15x15） |
| 包裝： | 托盤 |
| 其它名稱： | 336-1308 SI5100-G-BC-ND |
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Si5100
20
Rev. 1.5
Multiplier/Jitter Attenuator IC. Wideband operation
allows the DSPLL to more closely track the precision
reference source resulting in the best possible jitter
performance.
6.2. Serialization
The Si5100 serialization circuitry is comprised of a FIFO
and a parallel to serial shift register. The device can be
configured to serialize either 4-bit data words input on
TXDIN[3:0] or 16-bit data words input on TXDIN[15:0].
The 4-bit or 16-bit configuration is selected using the
MODE16 input. Low-speed data on the parallel input
bus is latched into the FIFO on the rising edge of
TXCLK16IN. Data is clocked out of the FIFO and into
the shift register by TXCLK16OUT. The high-speed
serial data stream TXDOUT is clocked out of the shift
register by TXCLKOUT. The TXCLK16OUT clock is
provided as an output signal to support either 4-bit or
16-bit word transfers between the Si5100 and upstream
devices using a counter clocking scheme.
6.2.1. Input FIFO
The Si5100 transmit FIFO decouples the timing of the
data transferred into the FIFO via TXCLK16IN from the
data transferred into the shift register via TXCLK16OUT.
The
FIFO
is
eight
parallel
words
deep
and
accommodates
static
phase
delay
that
may
be
introduced between TXCLK16OUT and TXCLK16IN in
counter clocking schemes. Furthermore, the FIFO
accommodates a bounded phase drift, or wander,
between TXCLK16IN and TXCLK16OUT of up to three
parallel data words.
The FIFO circuitry indicates an overflow or underflow
condition by asserting the FIFOERR signal. This output
can be used to re-center the FIFO read/write pointers by
tieing it directly to the FIFORST input.
The FIFORST signal causes re-centering of the FIFO
read/write pointers. The Si5100 also automatically re-
centers the read/write pointers after the device is
powered on, after an external reset via the RESET
input, and each time the DSPLL transitions from an out-
of-lock state to a locked state (when TXLOL transitions
from low to high).
6.2.2. Parallel Input To Serial Output Relationship
The Si5100 provides the capability to select the order in
which the data received on the parallel input bus,
TXDIN[15:0], is transmitted serially on the high-speed
serial data output, TXDOUT. Data on the parallel bus is
transmitted MSB first or LSB first depending on the
setting of the TXMSBSEL input. When TXMSBSEL is
set low, TXDIN0 is transmitted first, followed in order by
TXDIN1 through TXDIN15 (TXDIN1 through TXDIN3 if
MODE16 = 0). When TXMSBSEL is set high, TXDIN15
(TXDIN3) is transmitted first, followed in order by
TXDIN14 (TXDIN2) through TXDIN0. This feature can
simplify
printed
circuit
board
(PCB)
routing
in
applications where ICs are mounted on both sides of
the PCB.
6.2.3. Transmit Data Squelch
To prevent the transmission of corrupted data into the
network, the Si5100 provides a control pin that can be
used to force the high-speed serial data output
TXDOUT to zero. When the TXSQLCH input is set low,
the TXDOUT signal is forced to a zero state. The
TXSQLCH input is ignored when the device is in line
loopback mode (LLBK = 0).
6.2.4. Clock Disable
The Si5100 provides a clock disable pin, TXCLKDSBL,
that can be used to disable the high-speed serial data
clock output, TXCLKOUT. When the TXCLKDSBL pin is
asserted, the positive and negative terminals of
CLKOUT are internally tied to 1.5 V through 50
on-
chip resistors.
This feature can be used to reduce power consumption
in applications that do not use the high-speed transmit
data clock.
7. Loop Timed Operation
The Si5100 can be configured to provide SONET/SDH
compliant loop timed operation. When the LPTM input is
set low, the transmit clock and data timing is derived
from the CDR recovered clock output. This is achieved
by dividing down the recovered clock and using it as a
reference source for the transmit CMU. This results in
transmit clock and data signals that are locked to the
timing recovered from the received data path. A narrow-
band loop filter setting is recommended for this mode of
operation.
8. Diagnostic Loopback
The Si5100 provides a diagnostic loopback mode that
establishes a loopback path from the serializer output to
the deserializer input. This provides a mechanism for
looping back data input via the low-speed transmit
interface, TXDIN[15:0], to the low-speed receive data
interface, RXDOUT[15:0]. This mode is enabled when
the DLBK input is set low.
Note: Setting both DLBK and LLBK low simultaneously is not
supported.
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