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參數(shù)資料
| 型號： | SI5316-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR SI5316 |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | SI5316 |
| 已供物品： | 板，線纜，CD，文檔 |
Si5316
18
Rev. 1.0
21
CS
I
LVCMOS
Input Clock Select.
This pin functions as the input clock selector. This input is internally
deglitched to prevent inadvertent clock switching during changes in
the CKSEL input state.
0 = Select CKIN1
1 = Select CKIN2
Must be driven high or low.
23
22
BWSEL1
BWSEL0
I
3-Level*
Bandwidth Select.
Three level inputs that select the DSPLL closed loop bandwidth.
Detailed operations and timing characteristics for these pins may be
found in the Any-Frequency Precision Clock Family Reference Man-
ual.
These pins are both pull-ups and pull-downs and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
25
24
FRQSEL
1
FRQSEL
0
I
3-Level*
Frequency Select.
Sets the output frequency of the device. When the frequency of
CKIN1 is not equal to CKIN2, the lower frequency input clock must
be equal to the output clock frequency. These pins have both weak
pull-ups and weak pull-downs and default to M. For the pin settings,
see Table 3 on page 8.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
26
CK1DIV
I
3-Level*
Input Clock 1 Pre-Divider Select.
Pre-divider on CKIN1. Used with CK2DIV to divide input clock
frequencies to a common value.
L = CKIN1 input divider set to 1.
M = CKIN1 input divider set to 4.
H = CKIN1 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
27
CK2DIV
I
3-Level*
Input Clock 2 Pre-Divider Select.
Pre-divider on CKIN2. Used with CK1DIV to divide input clock
frequencies to a common value.
L = CKIN2 input divider set to 1.
M = CKIN2 input divider set to 4.
H = CKIN2 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Table 8. Si5316 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5317 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5317A-C-GM | 功能描述:標準時鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| SI5317A-C-GMR | 功能描述:時鐘合成器/抖動清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| Si5317B-C-GM | 功能描述:標準時鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| SI5317B-C-GMR | 功能描述:時鐘合成器/抖動清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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