tDC SCLK = 10 MHz 40 鈥� 60 % Cycle Time, SCLK
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� SI5324B-C-GM
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 6/72闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CLOCK MULT 2KHZ-808MHZ 36VQFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 490
绯诲垪锛� DSPLL®
椤炲瀷锛� 鏅�(sh铆)閻�/闋荤巼鍊嶅鍣�锛屾姈鍕曡“娓涘櫒锛屽璺京(f霉)鐢ㄥ櫒
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杓稿叆锛� 鏅�(sh铆)閻�
杓稿嚭锛� CML锛孋MOS锛孡VDS锛孡VPECL
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 2:2
宸垎 - 杓稿叆:杓稿嚭锛� 鏄�/鏄�
闋荤巼 - 鏈€澶э細 808MHz
闆绘簮闆诲锛� 1.71 V ~ 3.63 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 36-VFQFN 瑁搁湶鐒婄洡
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 36-QFN锛�6x6锛�
鍖呰锛� 鎵樼洡
Si5324
14
Rev. 1.1
SPI Specifications
Duty Cycle, SCLK
tDC
SCLK = 10 MHz
40
鈥�
60
%
Cycle Time, SCLK
tc
100
鈥�
ns
Rise Time, SCLK
tr
20鈥�80%
鈥�
25
ns
Fall Time, SCLK
tf
20鈥�80%
鈥�
25
ns
Low Time, SCLK
tlsc
20鈥�20%
30
鈥�
ns
High Time, SCLK
thsc
80鈥�80%
30
鈥�
ns
Delay Time, SCLK Fall
to SDO Active
td1
鈥斺€�
25
ns
Delay Time, SCLK Fall
to SDO Transition
td2
鈥斺€�
25
ns
Delay Time, SS Rise
to SDO Tri-state
td3
鈥斺€�
25
ns
Setup Time, SS to
SCLK Fall
tsu1
25
鈥�
ns
Hold Time, SS to
SCLK Rise
th1
20
鈥�
ns
Setup Time, SDI to
SCLK Rise
tsu2
25
鈥�
ns
Hold Time, SDI to
SCLK Rise
th2
20
鈥�
ns
Delay Time between
Slave Selects
tcs
25
鈥�
ns
Table 4. Microprocessor Control (Continued)
(VDD = 1.8 卤 5%, 2.5 卤10%, or 3.3 V 卤10%, TA = 鈥�40 to 85 掳C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
SI5324B-C-GMR 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊娓呴櫎鍣� Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
Si5324C-C-GM 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊娓呴櫎鍣� Prec.Clk Mult/Jitter Atten. 2kHz-346MHz RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
SI5324C-C-GMR 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊娓呴櫎鍣� Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
Si5324D-C-GM 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊娓呴櫎鍣� Prec.Clk Mult/Jitter Atten. 2kHz-150MHz RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel
SI5324D-C-GMR 鍔熻兘鎻忚堪:鏅�(sh铆)閻樺悎鎴愬櫒/鎶栧嫊娓呴櫎鍣� Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:鍚� 鍒堕€犲晢:Skyworks Solutions, Inc. 杓稿嚭绔暩(sh霉)閲�: 杓稿嚭闆诲钩: 鏈€澶ц几鍑洪牷鐜�: 杓稿叆闆诲钩: 鏈€澶ц几鍏ラ牷鐜�:6.1 GHz 闆绘簮闆诲-鏈€澶�:3.3 V 闆绘簮闆诲-鏈€灏�:2.7 V 灏佽 / 绠遍珨:TSSOP-28 灏佽:Reel