Si5330
Rev. 1.1
19
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Clarified documentation to reflect that Pin 19 is OEB
(OE Enable Low).
Updated Table 4, “Jitter Specifications” on page 7.
Revision 0.2 to Revision 0.3
Major editorial updates to improve clarity.
Updated “Additive Jitter” Specification Table.
Updated “Core Supply Current” Specification in
Removed the Low-Power LVPECL output options
from the ordering table in section
5.
Removed D/E ordering options.
Revision 0.3 to Revision 0.35
Typo of 150 ps on front page changed to 150 fs.
Updated PCB layout notes.
Added no ac coupling for LVDS outputs.
Changed input rise/fall time spec to 2 ns.
Revision 0.35 to Revision 1.0
Added maximum junction temperature specification
Added minimum and maximum duty cycle
Added maximum propagation delay spec (4 ns).
Removed reference to frequency in Output-Output
Skew.
Input voltage (max) changed “3.63” to “VDD”
Input voltage swing (max) change “3.63” with “—”.
Added tape and reel ordering information to
"5.Revision 1.0 to Revision 1.1
Updated ordering information to refer to revision B
silicon.
Updated top marking explanation in section
8.2.