參數(shù)資料
型號(hào): SI5330A-A00202-GM
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 9/20頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFFER TRANSLA 1:4 24-QFN
標(biāo)準(zhǔn)包裝: 490
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,CMOS,HCSL,HSTL,LVDS,LVPECL,LVTTL,SSTL
輸出: LVPECL
頻率 - 最大: 710MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 管件
Si5330
Rev. 1.1
17
7. Recommended PCB Layout
Table 13. PCB Land Pattern
Dimension
Min
Nom
Max
P1
2.50
2.55
2.60
P2
2.50
2.55
2.60
X1
0.20
0.25
0.30
Y1
0.75
0.80
0.85
C1
3.90
C2
3.90
E0.50
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on the IPC-7351 guidelines.
4.
Connect the center ground pad to a ground plane with no less than five vias to a ground plane that is no more than
20 mils below it. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is allowed if
more vias are used to keep the inductance from increasing.
Solder Mask Design
5.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60 m minimum, all the way around the pad.
Stencil Design
6.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7.
The stencil thickness should be 0.125 mm (5 mils).
8.
The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9.
A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10.
A No-Clean, Type-3 solder paste is recommended.
11.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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SI5330A-A00203-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
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