參數(shù)資料
型號(hào): SI5350A-A-GT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 3/22頁(yè)
文件大小: 0K
描述: IC CLK GEN PLL BLANK CUST 10MSOP
標(biāo)準(zhǔn)包裝: 50
系列: MultiSynth™
類型: *
PLL:
輸入: 晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 125MHz
除法器/乘法器: 是/無
電源電壓: 2.25 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
Si5350A
Rev. 0.9
11
Figure 6. Available Spread Spectrum Profiles
4.2.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
4.2.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350A as described in “4.3.4. Output Enable
(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as one of the
following: disable low, disable high, or disable in high-impedance.
4.2.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
4.3. Programmable Control Pins (P0–P4) Options
Up to five programmable control pins (P0-P4) are configurable allowing direct pin control of the following features:
4.3.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
4.3.2. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350A to minimize power consumption when its
output clocks are not being used. The Si5350A is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 2 on
4.3.3. Frequency Select (FS_0, FS_1)
The Si5350A offers the option of configuring up to two frequencies per clock output on CLK0-CLK5. This is a useful
feature for applications that need to support more than one clock rate on the same output. An example of this is
shown in Figure 7 where the FS pins selects which frequency is generated from the clock output: F1_0 is
generated when FS is set low, and F2_0 is generated when FS is set high.
Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output
fc
R educed
Am plitude
and E M I
Down S pread
fc
No Spread
Spectrum
Center
Frequency
Am plitude
Video
Processor
27 MHz
XA
XB
CLK0
FS0
Si5350A
74.25
1.001
MHz
or
MHz
Output Frequency Selected
FS0
Bit Level
0
1
74.25 MHz
F1_0:
F2_0:
74.25
1.001
MHz
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