
Si5350A
Rev. 0.9
5
Table 4. Input Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Crystal Frequency
fXTAL
25
—
27
MHz
P0-P4 Input Low Voltage
VIL-P0-4
–0.1
—
0.3 x VDD
V
P0-P4 Input High Voltage
VIH_P0-4
0.7 x VDD
—3.60
V
Table 5. Output Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Frequency Range
FCLK
0.008
—
160
MHz
Load Capacitance
CL
FCLK < 100 MHz
—
5
15
pF
Duty Cycle
DC
Measured at VDD/2
45
50
55
%
Rise/Fall Time
tr/tf
20%–80%, CL = 5 pF
0.5
1
1.5
ns
Output High Voltage
VOH
VDD – 0.6
—
V
Output Low Voltage
VOL
——
0.6
V
Period Jitter
JPER
Measured over 10k cycles
—
60
100
ps pk-pk
Cycle-to-Cycle Jitter
JCC
Measured over 10k cycles
—
50
90
ps pk
RMS Phase Jitter
JRMS
12 kHz–20 MHz
—
5.0
10
ps rms
Table 6. 25 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
—25—
MHz
Load Capacitance
CL
6—
12
pF
Equivalent Series Resistance
rESR
——
150
Crystal Max Drive Level
dL
——
150
W
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors. Adding external 2 pF load
capacitors can minimize jitter by 20%.
2. Refer to “AN551: Crystal Selection Guide” for more details.