參數(shù)資料
型號: SI5367B-C-GQR
廠商: Silicon Laboratories Inc
文件頁數(shù): 74/80頁
文件大?。?/td> 0K
描述: IC CLOCK MULTIPLIER PROG 100TQFP
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時鐘乘法器
PLL:
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 808MHz
除法器/乘法器: 無/是
電源電壓: 1.71 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 帶卷 (TR)
Si5367
76
Rev. 0.5
Table 13. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e0.50 BSC.
E
15.40 REF.
D
15.40 REF.
E2
3.90
4.10
D2
3.90
4.10
GE
13.90
GD
13.90
X
0.30
Y1.50 REF.
ZE
16.90
ZD
16.90
R1
0.15 REF
R2
1.00
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
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Si5367C-B-GQ 功能描述:時鐘合成器/抖動清除器 uP-PROGRAMMABE CLK MULT 10 MHZ-346 MHZ RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SI5367C-B-GQR 制造商:Silicon Laboratories Inc 功能描述:
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