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參數(shù)資料
| 型號(hào)： | SiI150ACT100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PanelLink Digital Transmitter |
| 中文描述： | PanelLink數(shù)字發(fā)射機(jī) |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 73K |
| 代理商： | SII150ACT100 |
Revision C
Subject to Change without Notice
Si
I
150A
PanelLink
Digital Transmitter
July 2000
General Description
Features
As the universal transmitter, S
iI
150A uses PanelLink Digital technology
to support displays ranging from VGA to SXGA (25-112 MHz). The S
iI
150A
transmitter supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or
2 pixels/clock mode, and also features an inter-pair skew tolerance up to 1 full
input clock cycle. An advanced on-chip jitter filter is also added to extend
tolerance to VGA clock jitter. Since all PanelLink products are designed on
scaleable CMOS architecture to support future performance requirements
while maintaining the same logical interface, system designers can be
assured that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
Scaleable Bandwidth: 25-112 MHz (VGA to SXGA)
Low Power: 3.3V core operation & power-down
mode
High Skew Tolerance: 1 full input clock cycle (9ns at
108 MHz)
Flexible panel interface: single or dual pixel in at up
to 24-bits
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards
compatible with VESA P&D
and DFP)
Si
I
150A Pin Diagram
Functional Block Diagram
Data
Capture
Logic
DE
HSYNC
VSYNC
CTL1
CTL2
CTL3
EDGE
PIXS
IDCK
EXT_SWING
Tx0
DATA
HSYNC
VSYNC
DATA
24
DIE[23:0]
DIO[23:0]
Encoder
0
Encoder
1
Encoder
2
CTL1
DATA
CTL2
CTL3
24
Jitter
Filter
PLL
Swing
Control
Tx1
Tx2
TxC
Tx0+
Tx0-
Tx1+
Tx1-
Tx2+
Tx2-
TxC+
TxC-
DIE13
1
SiI150A
100-Pin TQFP
(Top View)
DIE12
2
DIE11
3
DIE10
4
DIE9
5
DIE8
6
GND
7
VCC
8
DIE7
9
DIE6
10
DIE5
11
DIE4
12
DIE3
13
DIE2
14
DIE1
15
DIE0
16
IVCC
17
PVCC1
18
PGND1
19
RESERVED
20
RESERVED
21
RESERVED
22
RESERVED
23
EDGE
24
PIXS
25
P
2
R
2
R
2
R
2
V
3
G
3
E
3
A
3
T
3
T
3
A
3
A
3
A
3
T
3
T
4
A
4
T
4
T
4
A
4
T
4
T
4
A
4
D
4
D
4
D
5
75
DIO1
74
DIO2
73
DIO3
72
DIO4
71
DIO5
70
DIO6
69
DIO7
68
GND
67
IVCC
66
DIO8
65
DIO9
64
DIO10
63
DIO11
62
DIO12
61
DIO13
60
DIO14
59
DIO15
58
GND
57
VCC
56
DIO16
55
DIO17
54
DIO18
53
DIO19
52
DIO20
51
DIO0
D
1
D
9
I
9
D
9
D
9
D
9
D
9
D
9
D
9
D
9
D
9
G
8
V
8
R
8
P
8
P
8
C
8
C
8
C
8
I
8
I
8
G
7
D
7
V
7
H
7
DIFFERENTIAL
SIGNAL
O
EVEN 8-bits RED
O
E
O
E
C
P
PLL
CONTROLS
I
GPI
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