參數(shù)資料
型號(hào): SKY72300-21
廠商: Skyworks Solutions Inc
文件頁(yè)數(shù): 18/22頁(yè)
文件大小: 0K
描述: IC SYNTHESIZER 2.1GHZ 28-EPTSSOP
產(chǎn)品目錄繪圖: 28-TSSOP
標(biāo)準(zhǔn)包裝: 1
類型: 分?jǐn)?shù) N 合成器
PLL:
輸入: 時(shí)鐘,晶體
輸出: 時(shí)鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.173",4.40mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TSSOP 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 587 (CN2011-ZH PDF)
其它名稱: 863-1076-6
DATA SHEET SKY72300-21 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101217N Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 11, 2009
5
Fractional-N Applications. The desired division ratio for the
main and auxiliary synthesizers is given by:
ref
_
div
VCO
fractional
F
N
where Nfractional must be between 37.5 and 537.5.
The value to be programmed by the Main or Auxiliary Divider
Register is given by:
32
)
N
(
Round
N
fractional
reg
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for Nreg are from 6 to 505
inclusive.
The value to be programmed by either of the MSB/LSB Dividend
Registers or the Auxiliary Dividend Register is given by:
)]
32
N
(
divider
[
Round
dividend
reg
fractional
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
NOTE: Because of the high fractionality of the SKY72300-21,
there is no practical need for any integer relationship
between the reference frequency and the channel spacing
or desired VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
Integer-N Applications. The desired division ratio for the main or
auxiliary synthesizer is given by:
ref
_
div
main
_
vco
eger
int
F
N
where Ninteger is an integer number from 32 to 543.
The value to be programmed by the Main or Auxiliary Divider
Register is given by:
32
N
eger
int
reg
When in integer mode, allowed values for Nreg are from 0 to 511
for both the main and auxiliary synthesizers.
NOTE: As with all integer-N synthesizers, the minimum step size
is related to the crystal frequency and reference frequency
division ratio.
A sample calculation for an integer-N application is provided in
Figure 5.
Register Loading Order. In applications where the main
synthesizer is in 18-bit mode, the Main Dividend MSB Register
holds the 10 MSBs of the dividend and the Main Dividend LSB
Register holds the 8 LSBs of the dividend. The registers that
control the main synthesizer’s divide ratio are to be loaded in the
following order:
Main Divider Register
Main Dividend LSB Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
In applications where the main synthesizer is in 10-bit mode, the
Main Dividend MSB Register holds the 10 bits of the dividend. The
registers that control the main synthesizer’s divide ratio are to be
loaded in the following order:
Main Divider Register
Main Dividend MSB Register (at which point the new divide ratio
takes effect)
For the auxiliary synthesizer, the Auxiliary Dividend Register holds
the 10 bits of the dividend. The registers that control the auxiliary
synthesizer’s divide ratio are to be loaded in the following order:
Auxiliary Divider Register
Auxiliary Dividend Register (at which point the new divide ratio
takes effect)
NOTE: When in integer mode, the new divide ratios take effect as
soon as the Main or Auxiliary Divider Register is loaded.
Direct Digital Modulation
The high fractionality and small step size of the SKY72300-21
allow the user to tune to practically any frequency in the VCO’s
operating range. This allows direct digital modulation by
programming the different desired frequencies at precise instants.
Typically, the channel frequency is programmed by the Main
Divider and MSB/LSB Dividend Registers, and the instantaneous
frequency offset from the carrier is programmed by the
Modulation Data Register.
The Modulation Data Register can be accessed in three ways as
defined in the following subsections.
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