參數(shù)資料
型號: SL28504BZC-2
廠商: Silicon Laboratories Inc
文件頁數(shù): 12/27頁
文件大?。?/td> 0K
描述: IC CLOCK GEN EAGLELAKE 56TSSOP
標準包裝: 35
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:19
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
SL28504-2
........................ DOC #: SP-AP-0051 (Rev. AA) Page 2 of 27
56-TSSOP Pin Definitions
Pin No.
Name
Type
Description
1
PCI_0/ CR#_A
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 0 or
SRC 2. Default PCI_0
2
VDD_PCI
PWR
3.3V Power supply for PCI PLL.
3
PCI_1/ CR#_B
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 1 or
SRC 4. Default PCI_1.
4
PCI_2
O, SE 33 MHz clock.
5
PCI_3
O, SE, 33 MHz clock.
6
PCI4 /SRC5_EN
I/O, SE 33 MHz clock output/3.3V-tolerant input for SRC enable
(Sampled on CKPWRGD assertion)
1 = SRC5, 0 =CPU_STOP#/PCI_STOP#
7
PCIF_0/ITP_EN
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled
on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND
Ground for outputs.
9
VDD_48
PWR
3.3V Power supply for outputs and PLL.
10
USB_48/FSA
I/O
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer
to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
11
VSS_48
GND
Ground for outputs.
12
VDD_IO
PWR
3.3V-1.05V Power supply for outputs.
13
SRC0/DOT96T
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
14
SRC0#/DOT96#
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
15
VSS_IO
GND
Ground for PLL2.
16
VDD_PLL3
PWR
3.3V Power supply for PLL3
17
SRC1/25M0_F
O, SE 100 MHz Differential serial reference clocks/ Free run 25MHz clock output
18
SRC1#/25M1_24.576M
O, SE 100 MHz Differential serial reference clocks/ 25MHz clock output/24.576MHz clock
output
19
VSS_PLL3
GND
Ground for PLL3.
20
VDD_PLL3_IO
PWR
3.3V-1.05V power supply for PLL3
21
SRC2_SATA
O, DIF 100 MHz Differential serial reference clocks.
22
SRC2#_SATA#
O, DIF 100 MHz Differential serial reference clocks.
23
VSS_SRC
GND
Ground for outputs.
24
SRC3/ CR#_C
I/O,
Dif
100-MHz Differential serial reference clocks / 3.3V CR#_C, input, mappable via
I2C to control either SRC 0 or SRC 2. Default SRC3
25
SRC3#/ CR#_D
I/O,
Dif
100-MHz Differential serial reference clocks / 3.3V CR#_D input, mappable via I2C
to control either SRC 1 or SRC 4. Default SRC3
26
VDD_SRC_IO
PWR
3.3V-1.05V power supply for SRC outputs.
27
SRC4
O, DIF 100 MHz Differential serial reference clocks.
28
SRC4#
O, DIF 100 MHz Differential serial reference clocks.
29
CPU_STOP#/SRC5#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference
clocks. The option is selected by SRC5_EN
30
PCI_STOP#/SRC5
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs./100 MHz Differential serial
reference clocks.The option is selected by SRC5_EN
31
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
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