參數(shù)資料
型號: SL28506BZI-2T
廠商: Silicon Laboratories Inc
文件頁數(shù): 5/27頁
文件大?。?/td> 0K
描述: IC CLOCK CK505 PCIE GEN2 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:19
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
SL28506-2
.......................DOC #: SP-AP-0021 (Rev AB) Page 13 of 27
The SL28506-2 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal causes the SL28506-2 to
operate at the wrong frequency and violates the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires, etc.)
Dial-A-Frequency (CPU andSRC)
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Table 6. Output Driver Status
All Single-ended Clocks
All Differential Clocks except
CPU1
w/o Strap
w/ Strap
Clock
Clock#
Clock
Clock#
Latches Open State
Low
Hi-z
Low or 20K pulldown
Low
Low or 20K pulldown Low
Powerdown
Low
Hi-z
Low or 20K pulldown
Low
Low or 20K pulldown Low
M1
Low
Hi-z
Low or 20K pulldown
Low
Running
Table 7. Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
Figure 1. Crystal Capacitive Clarification
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
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