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參數(shù)資料
| 型號(hào)： | SL28540ALCT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, QFN-56 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 267K |
| 代理商： | SL28540ALCT |
SL28540
Rev 1.2, September 15, 2008
Page 2 of 25
Pin Definitions
Pin No.
Name
Type
Description
1
Xout
O, SE 14.318 MHz Crystal output.
2
Xin
I
14.318 MHz Crystal input.
3
VDD_REF
PWR
3.3V Power supply for outputs and maintains SMBUS registers during power
down.
4
REF0 / FSC / TEST_SEL
I/O
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency selection/
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifica-
tions.
5
SDATA
I/O
SMBus compatible SDATA.
6
SCLK
I
SMBus compatible SCLOCK.
7
PCI0 / CR#_A
I/O, SE 33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0.
To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair
0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6:
0 = CR#_A controls SRC0 pair (default)
1= CR#_A controls SRC2 pair
8
VDD_PCI
PWR
3.3V power supply for PCI PLL
9
PCI1 / CR#_B
I/O, SE 33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1.
To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair
4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4:
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
10
PCI2
O, SE 33 MHz Clock output/3.3V-tolerant input for enabling Trusted Mode
11
PCI3
O, SE 33 MHz Clock output
11, 12
PCI 4/GCLK_SEL
I/O, SE
PD
33 MHz Clock output/3.3V-tolerant input for selecting clock source on pin 23,
24.
Sampled at CKPWRGD assertion:
0 = SRC1(default), 1 = LCD_100M
Internal weak pull-down to GND
13
PCIF0 / ITP_EN
I/O, SE 33 MHz free running clock output/3.3V LVTTL input to enable SRC8 or
CPU2_ITP (sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
14
VSS_PCI
GND
Ground for outputs.
15
VDD_48
PWR
3.3V power supply for outputs and PLL.
16
USB_48 / FSA
I/O
Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
17
VSS_48
GND
Ground for outputs.
18
VDD_IO
PWR
3.3V-1.05V power supply for outputs
19
DOT96T
O, DIF Fixed True 96 MHz clock output.
20
DOT96C
O, DIF Fixed complement 96 MHz clock output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL28541BQCR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina, Atom RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28541BQCRT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina, Atom RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28541BZC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28541BZC-2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina, Atom RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28541BZC-2T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina, Atom RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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