- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9628 > SL28773ELC (Silicon Laboratories Inc)IC CLOCK CK505 PCIE INTEL 32QFN PDF資料下載
參數(shù)資料
| 型號： | SL28773ELC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 3/21頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK505 PCIE INTEL 32QFN |
| 標準包裝： | 624 |
| 系列： | EProClock® |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 133MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28773
...................... Document #: 001-08400 Rev ** Page 11 of 21
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires, etc.)
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPU clocks, all single-ended outputs will be held LOW on
their next HIGH-to-LOW transition and differential clocks must
held LOW. When PD# mode is desired as the initial power on
state, PD# must be asserted LOW in less than 10
s after
asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from are driven high in less than 300
s of
PD# deassertion to a voltage greater than 200 mV. After the
clock chip’s internal PLL is powered up and locked, all outputs
are enabled within a few clock cycles of each clock. Figure 4
is an example showing the relationship of clocks coming up.
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
Figure 3. Power Down Assertion Timing Waveform
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EL1506CREZ-T13 | IC LINE DRVR DUAL ADSL 28-HTSSOP |
| VE-J1K-MX-F3 | CONVERTER MOD DC/DC 40V 75W |
| EL1506CREZ | IC LINE DRVR DUAL ADSL 28-HTSSOP |
| EL1506CRE-T7 | IC LINE DRVR DUAL ADSL 28-HTSSOP |
| EL1506CRE-T13 | IC LINE DRVR DUAL ADSL 28-HTSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL28773ELCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Comm app w/PCIe requirements & Intel RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28773ELI | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Comm app w/PCIe requirements & Intel RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28773ELIT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Comm app w/PCIe requirements & Intel RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28774ELC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28774ELCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。