參數資料
型號: SL28DB200AZIT
廠商: Silicon Laboratories Inc
文件頁數: 3/8頁
文件大?。?/td> 0K
描述: IC CLOCK PCIE DIFF 2CH 16TSSOP
標準包裝: 2,500
類型: 扇出緩沖器(分配)
PLL:
主要目的: PCI Express(PCIe),SATA CPU
輸入: 時鐘
輸出: HCSL
電路數: 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 210MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應商設備封裝: *
包裝: *
SL28DB200
........................ Document #: 38-07722 Rev 0.4 Page 3 of 8
Output Enable Clarification
OE# functionality allows for enabling and disabling individual
outputs. OE1# and OE2# are Active LOW inputs. Disabling the
outputs may be implemented by deasserting the OE# input
pin. If the OE# pin is deasserted, the output of interest will be
tri-stated. (The assertion and deassertion of this signal is
absolutely asynchronous.)
OE Assertion
All differential outputs that were tri-stated will resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2–6 SRC clock
periods. In addition, SRC clocks will be driven high within 15
ns of OE# assertion to a voltage greater than 200 mV
Absolute Maximum Conditions
OE Deassertion
The impact of deasserting OE# is that each corresponding
output will transition from normal operation to tri-state in a
glitch-free
manner.
The
maximum
latency
from
the
deassertion to tri-stated outputs is between 2–6 DIF clock
periods.
DC Electrical Specifications
Table 2. OE Functionality
OE#
SRC,SRC#
0
Enable
1
Tri-State
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDDA
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
(Commercial Grade)
Functional
0
85
°C
TA
Temperature, Operating Ambient
(Industrial Grade)
Functional
-40
85
°C
TJ
Temperature, Junction
Functional
150
°C
ESDHBM
ESD Protection (Human Body Model)
JEDEC (JESD 22 - A114)
2000
V
UL-94
Flammability Rating
UL (Class)
V–0
Parameter
Description
Condition
Min.
Max.
Unit
VDDA,
VDD
3.3V Operating Voltage
3.3 ± 5%
3.135
3.465
V
VIL
3.3V Input Low Voltage
VSS – 0.5
0.8
V
VIH
3.3V Input High Voltage
2.0
VDD + 0.5
V
IIL
Input Low Leakage Current
except internal pull-up resistors, 0 < VIN < VDD
–5
A
IIH
Input High Leakage Current
except internal pull-down resistors, 0 < VIN < VDD
5
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
–-
6
pF
LIN
Pin Inductance
7
nH
IDD3.3V
Dynamic Supply Current
At max. load, Full Active, at 100MHz
60
mA
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