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參數(shù)資料
| 型號： | SL28PCIE26ALC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK PCIE GEN3/2 32QFN |
| 標準包裝： | 624 |
| 系列： | EProClock® |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 100MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28PCIe26
DOC#: SP-AP-0774 (Rev. 0.2)
Page 8 of 14
.
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of SRCC, differential clocks must held LOW. When PD mode
is desired as the initial power on state, PD must be asserted
HIGH in less than 10
s after asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300
s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
.
40
OTP_4
OTP_ID
Idenification for programmed device
30
OTP_3
21
OTP_2
10
OTP_1
01
OTP_0
Bit
@Pup
Name
Description
Table 4. Output Driver Status
All Differential Clocks
Clock
Clock#
PD# = 0 (Power down)
Low
Figure 1. Power down Assertion Timing Waveform
Figure 2. Power down Deassertion Timing Waveform
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參數(shù)描述 |
|---|---|
| SL28PCIe26ALCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PCIE Clk Gen Xin 25M -->4 PCIE out Gen3 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28PCIe26ALI | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PCIE Clk Gen Xin 25M -->4 PCIE out Gen3 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28PCIe26ALIT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PCIE Clk Gen Xin 25M -->4 PCIE out Gen3 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28PCIe30ALC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 6outputs 3sngl ended 25MHz crystal input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28PCIe30ALCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 6outputs 3sngl ended 25MHz crystal input RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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