tF - 300 - 300 ns STOP set-up time
參數(shù)資料
型號(hào): SL38000ZC
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 12/12頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK SSCG 4PLL 9CH 28TSSOP
標(biāo)準(zhǔn)包裝: 50
系列: EProClock®
類型: *
PLL: 帶旁路
輸入: 時(shí)鐘,晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:11
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 200MHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.97 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
Rev 1.1, August 7, 2008
Page 9 of 12
SL38000
SDA/SCLK
fall time
tF
-
300
-
300
ns
STOP set-up
time
tSU;STO
4.0
-
0.6
-
ns
Bus free time
tBUF
4.7
-
1.3
-
μs
Table 2. I2C-Bus Timing Specification
I2C-Bus Timing Diagram
External Components & Design Considerations
Typical Application Schematic
TBD
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between all VDD and VSS pins on PCB.
Place the capacitor on the component side of the PCB as close to the VDD pins as possible. The PCB trace to the
VDD pins and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pins.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(CLKOUT or REFCLK pins) and the load is over 1 inch. The nominal impedance of the all clock outputs are about
25
Ω. Use 20 Ω resistor in series with the output to terminate 50Ω trace impedance and place 20 Ω resistor as close
to the SSCLK output as possible.
Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals.
To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and
PCout must be programmed to match the crystal load requirement. These values are given by the formula below:
tLOW
tF
tHD;STA
tR
tHD;DAT
tSU;DAT
tHIGH
tF
tSU;STA
tHD;STA
tSU;STO
tBUF
SDATA
SCLK
tR
S
Sr
P
S
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