參數(shù)資料
型號: SL38160ZCT
廠商: Silicon Laboratories Inc
文件頁數(shù): 9/11頁
文件大?。?/td> 0K
描述: IC CLOCK SSCG 4PLL 5CH 16TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: EProClock®
類型: *
PLL: 帶旁路
輸入: 時鐘,晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:5
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 無/無
電源電壓: 2.25 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
Rev 1.1, January 5, 2009
Page 7 of 11
SL38160
Output Low Voltage
VOL1
IOL=6mA , Pins programmed as
CLKOUT/REFOUT
-
0.5
V
Operating Supply
Current
IDD1
FIN=27MHz and all 5 clocks are
at 33MHz and CL=0,
VDD=VDDO=3.3V
-
TBD
mA
Operating Supply
Current
IDD2
FIN=27MHz and all 5 clocks are
at 33MHz and CL=0,
VDD=VDDO=2.5V
-
TBD
mA
Operating Supply
Current
IDD3
FIN=27MHz and all 5 clocks are
at 66MHz and CL=0
VDD=VDDO=3.3V
-
TBD
mA
Operating Supply
Current
IDD3
FIN=27MHz and all 5 clocks are
at 66MHz and CL=0
VDD=VDDO=2.5V
-
TBD
mA
Programmable XO
mode, Input Crystal
Load (CL) Capacitance
at Pins 1 and 16
Cin
Cout
Minimum setting value
-
12
-
pF
Maximum setting value
-
40
-
pF
Resolution (programming steps)
-
0.5
-
pF
Load Capacitance
CL
All CLKOUT outputs
-
15
pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD=VDD= 2.5 to 3.3V+/-10%, CL=15pF and Ambient Temperature range -40 to +85°C
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Frequency Range
FIN1
XO Mode, Fundamental Crystal
8
-
48
MHz
Input Frequency Range
FIN2
VCXO Mode, Pullable Crystal
13
27
30
MHz
Input Frequency Range
FIN3
External clock input, Pin 1
3
-
166
MHz
Output Frequency Range
FOUT1
Programmable CLKOUT, Pins 7, 8,
9,10 and 11, VDD=VDDO=3.3V
3
-
200
MHz
Output Frequency Range
FOUT2
Programmable CLKOUT, Pins 8,
9,10 and 11, VDD=VDDO=2.5V
3
-
166
MHz
Output Frequency Range
FOUT3
Programmable REFCLK, Pins 7, 8,
9,10 and 1, crystal input mode is
used
0.25
-
48
MHz
Output Frequency Range
FOUT4
Programmable REFCLK, Pins 7, 8,
9,10 and 1, crystal input mode and
CLKIN is used
0.25
-
166
MHz
Output Duty Cycle
DC1
CLKOUT, Pins 7, 8, 9,10 and 11
45
50
55
%
Output Duty Cycle
DC2
REFCLK, Pins 7, 8, 9,10 and 11
45
50
55
%
Input Duty Cycle
DCIN
Clock Input, Pin 3
30
50
70
%
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ1
FIN=27MHz crystal, all 5 clocks are
programmed at 33MHz, CL=10pF
-
TBD
ps
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ2
FIN=27MHz, all 5 clocks are
programmed at 66MHz, CL=10pF
-
TBD
ps
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