參數(shù)資料
型號: SL38160ZI
廠商: Silicon Laboratories Inc
文件頁數(shù): 10/11頁
文件大?。?/td> 0K
描述: IC CLOCK SSCG 4PLL 5CH 16TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: EProClock®
類型: *
PLL: 帶旁路
輸入: 時鐘,晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:5
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 無/無
電源電壓: 2.25 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
Rev 1.1, January 5, 2009
Page 8 of 11
SL38160
Power supply Ramp
Time
tPSR
Time for VDD reaching minimum
specified value and monolithic
power supply ramp
-
12
ms
PLL Lock Time
tPLL
Time from VDD reaching minimum
specified value to valid output
frequencies at all outputs
-
7.5
9.0
ms
Spread Percent Range
SPR-1
Center Spread
+/-0.125
-
+/-2.5
%
Spread Percent Range
SPR-2
Down Spread
-5.0
-
-0.25
%
Modulation Frequency
FMOD
Programmable, 31.5 kHz standard
25
31.5
120
kHz
VCXO Pull Range
ΔFVCXO VCXO Crystal Pull Range
+/-110
+/-120
-
ppm
Clock Output
Frequency Selection Pins
Selected Number of Frequencies
TBD
Table 1. Frequency Selection Options for Clock Outputs
Programmable Output Clock (CLKOUT) Rise and Fall Times
The output clock rise and fall times (tr/tf) of each clock output can be programmed independently to match drive level
to load impedance.
Programming
Code
VDDO=3.3V
CL=15pF
VDDO=2.5V
CL=15pF
Unit
000
4.00
4.80
ns
001
2.00
2.60
ns
010
1.40
1.80
ns
011
1.10
1.40
ns
100
0.85
1.10
ns
101
0.70
0.90
ns
110
0.55
0.70
ns
Table 2. Programmable CLKOUT Rise and Fall Times
Notes:
1. All typical values are at respective nominal VDD values.
2. The worst case rise and fall times variations are +/- 20% for C-Grade and +/-30% for I-grade.
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