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| 型號： | SLA24C02-S-3 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, DSO-8 |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 361K |
| 代理商： | SLA24C02-S-3 |
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SLx 24C01/02/P
Semiconductor Group
12
1998-07-27
5.2
Page Write
Those bytes of the page that have not been addressed are not included in the
programming.
Figure 8
Page Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3
Acknowledge Polling).
Address Setting
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address byte EEA is followed
by a sequence of one to maximum eight data bytes with the
new data to be programmed. These bytes are transferred to
the internal page buffer of the EEPROM.
The first entered data byte will be stored according to the
EEPROM address n given by EEA (A0 to A6 or A7). The
internal address counter is incremented automatically after the
entered data byte has been acknowledged. The next data byte
is then stored at the next higher EEPROM address. EEPROM
addresses within the same page have common page address
bits A2 through A6 or A7. Only the respective three least
significant address bits A0 through A2 are incremented, as all
data bytes to be programmed simultaneously have to be
within the same page.
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Transmission of Data
Programming Cycle
Command Byte
CSW
S
P
C
K
A
S
T
A
R
T
T
O
P
S
EEPROM Address
EEA n
Data Byte n
Data Byte n+1
Data Byte n+7
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02280
0
C
K
A
C
K
A
C
K
A
C
K
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SLX24C01 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| SLX24C04 | 4 Kbit 512 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLX24C0816 | 8/16 Kbit 1024/2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLX24C164 | 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLX24C32 | 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SLA24C02-S-3/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| SLA24C02-SR-3 | 制造商:Infineon Technologies AG 功能描述: |
| SLA24C04 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4 Kbit 512 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode |
| SLA24C04-D | 制造商:Siemens 功能描述:512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| SLA24C04-D/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4 Kbit 512 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode |
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