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| 型號(hào)： | SLA24C64-S-3 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, DSO-8 |
| 文件頁(yè)數(shù)： | 7/26頁(yè) |
| 文件大?。?/td> | 358K |
| 代理商： | SLA24C64-S-3 |
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SLx 24C64
Semiconductor Group
7
Preliminary 1998-07-27
3
Access to the SLx 24C64 device is given via the
I
2
C bus. This bidirectional bus consists
of two wires SCL and SDA for clock and data. The protocol is master/slave oriented,
where the serial EEPROM always takes the role of a slave.
I
2
C-Bus Characteristics
Figure 3
Bus Configuration
Master
Device that initiates the transfer of data and provides the clock for transmit
and receive operations.
Device addressed by the master, capable of receiving and transmitting
data.
Transmitter
The device using the SDA as output is defined as the transmitter. Due to
the open drain characteristic of the SDA output the device applying a low
level wins.
Receiver
The device using the SDA as input is defined as the receiver.
Slave
Slave 1
Slave 2
Slave 3
Slave 4
Slave 8
Slave 5
Slave 6
Slave 7
Master
V
CC
CC
V
IES02183
SCL
SDA
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|---|---|
| SLA24C64-S-3/P | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
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