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128 bit Identification Area consisting of
– 16 bit Manufacturer code (mask-programmable ROM)
– 8 bit Manufacturer data (ROM)
– 104 bit for personalization data of card issuer (PROM)
160 bit Value Counter (PROM/EEPROM)
16 bit secret User Code (EEPROM)
32 bit either secret Security Code or Data Area 3 in
Standard User Mode (EEPROM)
12 bit Data Area 1 (EEPROM)
32 bit Data Area 2 (EEPROM)
64 bit Response Counter
64 bit secret Authentication Key
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The memory is secured by different access codes dependent on the mode
– Issuer Mode: The memory access is secured by the 4 byte Transport Code
– Security User Mode: The memory access is secured by the 4 byte Security Code
– Standard User Mode: The memory access is secured by the 2 byte User Code. The
verification procedure is fully compatible with SLE 4404
The different chip modes are set by 3 flag bits.
Only after a successful code verification the chip logic allows to write or erase the data
according to the implemented functionality.
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– Three stage abacus counter
– Due to testing purposes a maximum of 127040 count units is guaranteed
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– 64 bit Random number as challenge
– 64 bit individual secret Authentication Key
– Calculation of up to 31 bit response within 60 ms at a clock frequency of 100 kHz
– Response calculation with cipher block chaining
– Authentication access and response calculation controlled by the Response Counter
– Four stage Response Counter with up to 69904 count units (61712 units guaranteed)
– Certification of the decreasing of the Value Counter
– Signature of the data content
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