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參數(shù)資料
| 型號： | SLVU2.8.TG |
| 元件分類： | TVS二極管 - 瞬態(tài)電壓抑制 |
| 英文描述： | 400 W, UNIDIRECTIONAL, SILICON, TVS DIODE |
| 封裝： | PLASTIC PACKAGE-3 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 126K |
| 代理商： | SLVU2.8.TG |
5
2003 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
SLVU2.8
SLVU2.8 Circuit Diagram
Protection of one unidirectional line
Device Connection Options
Electronic equipment is susceptible to transient distur-
bances from a variety of sources including: ESD to an
open connector or interface, direct or nearby lightning
strikes to cables and wires, and charged cables “hot
plugged” into I/O ports. The SLVU2.8 is designed to
protect sensitive components from damage and latch-
up which may result from such transient events. The
SLVU2.8 can be configured to protect either one
unidirectional line or two (one line pair) high-speed data
lines. The options for connecting the devices are as
follows:
1. Protection of one unidirectional I/O line: Protec-
tion of one data line is achieved by connecting pin
3 to the protected line, and pins 1 and 2 to ground.
This connection option will allow the device to
operate on lines with positive polarity signal transi-
tions (during normal operation). In this configura-
tion, the device adds a maximum loading capaci-
tance of 100pF. During positive duration tran-
sients, the internal TVS diode will be reversed
biased and will act in the avalanche mode, con-
ducting the transient current from pin 3 to 1. The
transient will be clamped at or below the rated
clamping voltage of the device. For negative
duration transients, the internal steering diode is
forward biased, conducting the transient current
from pin 2 to 3. The transient is clamped below
the rated forward voltage drop of the diode.
2. Low capacitance protection of one differential
line pair: Protection of a high-speed differential line
pair is achieved by connecting two devices in anti-
parallel. Pin 1 of the first device is connected to
line 1 and pin 2 is connected to line 2. Pin 2 of the
second device is connected to line 1 and pin 1 is
connected to line 2 as shown. Pin 3 must be left
open on both devices. During negative duration
transients, the first device will conduct from pin 2
to 1. The steering diode conducts in the forward
direction while the TVS will avalanche and conduct
in the reverse direction. During positive transients,
the second device will conduct in the same man-
ner. In this configuration, the total loading capaci-
tance is the sum of the capacitance (between pins
1 and 2) of each device (typically <10pF) making
this configuration suitable for high-speed interfaces
such as 10/100 Ethernet (See application note
SI98-02).
1
2
3
Low capacitance protection of one high-speed line
pair
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
"
Place the SLVU2.8 near the input terminals or
connectors to restrict transient coupling.
"
Minimize the path length between the TVS and the
protected line.
"
Minimize all conductive loops including power and
ground loops.
"
The ESD transient return path to ground should be
kept as short as possible.
"
Never run critical signals near board edges.
"
Use ground planes whenever possible.
Applications Information
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