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參數(shù)資料
| 型號： | SLX24C32 |
| 廠商： | SIEMENS AG |
| 英文描述： | 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 32千位4096 × 8位串行CMOS EEPROM的，I2C同步2線總線 |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 361K |
| 代理商： | SLX24C32 |
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SLx 24C01/02/P
Semiconductor Group
22
1998-07-27
7.3
The byte sequence for random bit read is shown in
figure 17
.
Protection Bit Read
Figure 17
Byte Sequence for Protection Bit Read
The first command byte CSW followed by the control byte EEA addresses the protection
bit to be read. The second command byte CSW is followed by the control byte 00
H
for
protection bit read. The first bit (MSB) of the transferred byte is the protection bit of the
addressed page. The other 7 bits are not valid. The page protection status is indicated
as following
Protection Bit = 1: A normal write operation changes the data in the associated page
Protection Bit = 0: The data in the associated page are protected against changes.
If the master acknowledges a byte with a low state of the SDA line, the protection bit of
the next page can be read as the first bit of the following byte. If the master releases the
SDA line, a STOP condition has to complete the read procedure. Any number of bytes
with a page protection status at the first bit position can be requested by the master. If
the bit of the uppermost page has been addressed, the counter has its overflow to the
lowest address according to the first page.
0
SDA Line
EEPROM
Bus Activity
Master
Bus Activity
EEA n
Address
EEPROM
CSW
Byte
Command
S
R
T
A
T
0
S
S
0
0 0 0
C
K
A
R
T
A
T
CSW
Byte
Command
S
Data
Byte n
0
C
K
A
CTR
Control
Byte
0
C
K
A
Data
Byte n+1
C
K
A
C
K
A
...
IED02139
P
C
K
A
O
P
T
S
b
b
b
K
C
A
b = Protection Bit
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|---|---|
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