
SGUS011D APRIL 1991 REVISED SEPTEMBER 2004
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Class B High-Reliability Processing
1-
μ
m CMOS Technology
Military Operating Temperature Range
55
°
C to 125
°
C
SMJ34020A-32/40
125/100-ns Instruction Cycle Time
Fully Programmable 32-Bit
General-Purpose Processor With
512-Megabyte Linear Address Range
(Bit Addressable)
Second-Generation Graphics System
Processor
Object-Code Compatible With the
SMJ34010
Enhanced Instruction Set
Optimized Graphics Instructions
Coprocessor Interface
Pixel Processing, XY Addressing, and
Window Checking Built Into the Instruction
Set
Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit
Pixel Size With 16 Boolean and Six
Arithmetic Pixel Processing Options
(Raster Ops)
512-Byte LRU On-Chip Instruction Cache
Optimized DRAM/VRAM Interface
Page-Mode for Burst Memory Operations
Dynamic Bus Sizing (16-Bit and
32-Bit Transfers)
Byte-Oriented CAS Strobes
Flexible Host Processor Interface
Supports Host Transfers
Direct Access to All of the SMJ34020A
Address Space
Implicit Addressing
Prefetch for Enhanced Read Access
Programmable CRT Control
Composite Sync Mode
Separate Sync Mode
Synchronization to External Sync
Direct Support for Special Features of
1M VRAMs
Load Write Mask
Load Color Mask
Block Write
Write Using the Write Mask
Flexible Multi-Processor Interface
Packaging Options
145-Pin Grid Array Ceramic Package
(GB Suffix)
132-Pin Ceramic Quad Flat Pack
(Unformed Lead) (HT Suffix)
145-PIN GRID ARRAY PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
132-PIN QUAD FLATPACK
(TOP VIEW)
1
1
99
3
1
6
33
67
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Copyright
2004, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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