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SM5165AV
NIPPON PRECISION CIRCUITS—7
Reference counter frequency divider setting
Bits 1 to 7 and bits 21 and 22 have no meaning. These bits should be set to 0.
Bits 8 and 9 are used for testing at the manufacturers and should be set to 1 and 0, respectively, for normal
operation.
Input data example
If the VCO output is (f
VCO
) trebled, the crystal oscillator frequency is 12.8 MHz and the channel bandwidth
(f
CH
: comparator frequency (f
R
)
×
3) is 25 kHz, then the reference frequency divider ratio R is given by:
Therefore, the reference counter count is 192 (00011000000)
2
.
Boost-up Signal
No
meaning
1
2
3
4
5
6
7
8
9
10
2
11
2
12
2
13
2
14
2
15
2
16
2
17
2
MSB
DATA
18
2
19
2
20
2
21
22
23
LSB
10
9
8
7
6
5
4
3
2
1
0
Reference counter
(11-bit : 5 to 8191)
Latch select bit. Set "0"
Test bits
No meaning
NR
f
CH
Xtal
f
R
3
--Xtal
0.025 3
-----12.8
1536
8
192
×
=
=
=
=
=
1
2
3
4
5
6
7
8
9
10
2
0
11
2
0
12
2
0
13
2
1
14
2
1
15
2
0
16
2
0
17
2
0
MSB
18
2
0
19
2
0
20
2
0
21
22
23
LSB
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
0
0
Input
Data
No
meaning
Reference counter
(11-bit : 5 to 8191)
Latch select bit. Set "0"
Test bits
No meaning
When the PLL starts up with some phase tolerance, a
level signal is output on pin DB. When the PLL
phase error comes within the tolerance before in
lock, output DB goes high impedance.
When the PLL starts up, the signal on DB charges
the low-pass filter capacitor in anticipation of high-
speed locking. After the boost-up signal is output and
the PLL phase error comes within tolerance, the
boost-up circuit stops and operation continues when
the 3 supplies (V
DD1
, V
DD2
) are applied and OPR
goes HIGH once only. After the boost-up circuit
stops, new data is written and the boost-up signal is
not output even if the VCO is not in lock.
FR
FV
Phase detector
error correction signal
WINDOWN
DB
(High impedance)
(High impedance)
(HIGH level output)
: 32f
FIN
(
)